Abstract:
A dynamic wafer alignment method and an exposure scanner system are provided. The exposure scanner system having a scan path, includes an exposure apparatus, an optical sensor apparatus and a wafer stage. The method comprises the steps of: (a) providing a wafer, having a plurality of shot areas, wherein each shot area has a plurality of alignment marks thereon; (b) forming a photo-resist layer on the wafer; (c) detecting the alignment marks at a portion of a shot area along the scan path by the optical sensor apparatus to obtain compensation data for wafer alignment of the portion of the shot area; (d) performing real time feedback of the compensation data for wafer alignment to the wafer stage; (e) exposing the photo-resist layer at the portion of the shot area along the scan path; (f) continuously repeating the steps (c) to (e) at the shot area along the scan path until all of the photo-resist layer at the shot area are exposed; and (g) repeating the step (f) until the photo-resist layer of all of the shot areas on the wafer are exposed.
Abstract:
An overlay mark set includes a substrate, a first overlay mark and a second overlay mark. The first overlay mark is disposed on the substrate for representing a first layout pattern. The second overlay mark is also disposed on the substrate for representing a second layout pattern. In particular, the first overlay mark is in direct contact with the second overlay mark.
Abstract:
A method of forming an overlay mark is provided. A plurality of photoresist patterns are formed on a substrate. Each of the photoresist patterns includes a first strip and a plurality of second strips arranged in parallel. The first strip crosses the second strips to form a fence shape. Further, there is a space between two adjacent photoresist patterns, and the space is fence-shaped. A plurality of islands are formed in each of the spaces to form dot type strip patterns. The photoresist patterns are removed, and the dot type strip patterns serve as the overlay mark.
Abstract:
A mark for alignment and overlay, a mask having the same, and a method of using the same are provided. The mark includes a first mark pattern and a second mark pattern. The first mark pattern includes a first pattern and a second pattern, and the second mark pattern includes a third pattern and a fourth pattern. The first pattern includes a plurality of rectangular regions arranged in a first direction, and for each rectangular region, a sideline in a second direction is longer than a sideline in the first direction, wherein the first direction is perpendicular to the second direction. The second pattern is disposed on both sides of the first pattern in the second direction and includes a plurality of rectangular regions arranged in the second direction, and for each rectangular region, the sideline in the first direction is longer than a sideline in the second direction. The third pattern includes two rectangular regions disposed on both sides of the first pattern in the first direction, and the fourth pattern includes two rectangular regions disposed on both sides of the second pattern in the second direction.
Abstract:
An integrated alignment and overlay mark includes a pre-layer pattern for reticle-to-wafer registration implemented in an exposure tool, and a current-layer pattern incorporated with the pre-layer pattern. The pre-layer pattern and the current-layer pattern constitute an overlay mark for determining registration accuracy between two patterned layers on a semiconductor wafer.
Abstract:
A mask overlay method, and a mask and a semiconductor device using the same are disclosed. According to the disclosed mask overlay technique, test marks and front layer overlay marks corresponding to a plurality of overlay mark designs are generated in a first layer of a semiconductor device. The test patterns generating the test marks each include a first sub pattern and a second sub pattern. Note that the first sub pattern has the same design as a front layer overlay pattern (which generates the front layer overlay mark corresponding thereto). Based on the test marks, performances of the plurality of overlay mark designs are graded. The front layer overlay mark corresponding to the overlay mark design having the best performance is regarded as an overlay reference for a mask of a second layer of the semiconductor device.
Abstract:
A method of forming an overlay mark is provided. A plurality of photoresist patterns are formed on a substrate. Each of the photoresist patterns includes a first strip and a plurality of second strips arranged in parallel. The first strip crosses the second strips to form a fence shape. Further, there is a space between two adjacent photoresist patterns, and the space is fence-shaped. A plurality of islands are formed in each of the spaces to form dot type strip patterns. The photoresist patterns are removed, and the dot type strip patterns serve as the overlay mark.
Abstract:
An integrated alignment and overlay mark includes a pre-layer pattern for reticle-to-wafer registration implemented in an exposure tool, and a current-layer pattern incorporated with the pre-layer pattern. The pre-layer pattern and the current-layer pattern constitute an overlay mark for determining registration accuracy between two patterned layers on a semiconductor wafer.