Overlay measurement system using lock-in amplifier technique

    公开(公告)号:US12124177B2

    公开(公告)日:2024-10-22

    申请号:US17782622

    申请日:2020-11-18

    Abstract: A detection system (200) includes an illumination system (210), a first optical system (232), a phase modulator (220), a lock-in detector (255), and a function generator (230). The illumination system is configured to transmit an illumination beam (218) along an illumination path. The first optical system is configured to transmit the illumination beam toward a diffraction target (204) on a substrate (202). The first optical system is further configured to transmit a signal beam including diffraction order sub-beams (222, 224, 226) that are diffracted by the diffraction target. The phase modulator is configured to modulate the illumination beam or the signal beam based on a reference signal. The lock-in detector is configured to collect the signal beam and to measure a characteristic of the diffraction target based on the signal beam and the reference signal. The function generator is configured to generate the reference signal for the phase modulator and the lock-in detector.

    METHOD FOR EVALUATING REFERENCE MARK FORMED ON EUV MASK BLANK

    公开(公告)号:US20240345474A1

    公开(公告)日:2024-10-17

    申请号:US18621633

    申请日:2024-03-29

    CPC classification number: G03F1/84 G03F7/70033 G03F7/70683 G03F9/7088

    Abstract: The present invention is a method for evaluating a reference mark formed on an EUV mask blank, the method including steps of: imaging the reference mark formed on the EUV mask blank to obtain a reference mark image; obtaining a reference mark contrast from the obtained reference mark image, the reference mark contrast being contrast between the reference mark and a background level; and evaluating processing accuracy of the reference mark with the obtained reference mark contrast. This provides a method for evaluating an EUV mask blank that can easily evaluate processing accuracy (for example, depth) of a reference mark.

    MULTI-OVERLAY STACKED GRATING METROLOGY TARGET

    公开(公告)号:US20240302751A1

    公开(公告)日:2024-09-12

    申请号:US18230542

    申请日:2023-08-04

    CPC classification number: G03F7/70633 G03F7/70625 G03F9/7088

    Abstract: An overlay metrology target includes a multi-layer grating structure formed as an overlapping grating structure with different pitches on three or more layers of a sample. The three or more layers of the sample may include at least a first layer, a second layer, and a third layer, where the overlapping grating structure is periodic along at least one of the scan direction or a direction orthogonal to the scan direction. The multi-layer grating structure may include a first-layer grating on the first layer with a first pitch, a second-layer grating on the second layer with a second pitch, and a third-layer grating on the third layer with a third pitch.

    Metrology system for packaging applications
    6.
    发明公开

    公开(公告)号:US20240241456A1

    公开(公告)日:2024-07-18

    申请号:US18098482

    申请日:2023-01-18

    CPC classification number: G03F9/7088 G03F7/70775 G03F9/7069

    Abstract: Methods and apparatus for detecting metrology data are provided herein. For example, an apparatus comprises a substrate support configured to support a substrate and another substrate disposed on the substrate, an incoherent light source configured to transmit an illumination beam through the substrate and the another substrate, a set of optics configured to direct the illumination beam when transmitted through the substrate and the another substrate, an actuator operably coupled to the substrate support and configured to move the substrate and another substrate back and forth in a scanning pattern, and a sensor operably coupled to the actuator, synchronized therewith, and configured to receive the illumination beam from the set of optics to obtain subsurface images of the substrate and the another substrate.

    EXPOSURE APPARATUS, EXPOSURE METHOD, DEVICE MANUFACTURING METHOD, AND DEVICE

    公开(公告)号:US20240184214A1

    公开(公告)日:2024-06-06

    申请号:US18286275

    申请日:2022-03-17

    Inventor: Yoji WATANABE

    CPC classification number: G03F7/70508 G03F7/70775 G03F9/7088

    Abstract: An exposure apparatus includes: a substrate stage onto which a substrate is to be mounted; an exposure unit radiating an exposure light toward the draw-out electrode on at least one semiconductor chip; a pattern determination unit determining an exposure pattern; and a controller controlling the substrate stage and the exposure unit. The pattern determination unit determines a pattern of a relay wiring connecting the draw-out electrode and a predetermined position with respect to the substrate, by using an output from a measurement unit to measure a position of the semiconductor chips on the substrate to obtain a positional deviation. The controller exposes the relay wiring pattern onto an exposure area extending, on the photosensitive layer, in the uniaxial direction by the exposure unit, while moving the substrate from a first-side in the uniaxial direction to a second-side opposite to the first-side in the uniaxial direction by the substrate stage.

    Detection apparatus, lithography apparatus, and article manufacturing method

    公开(公告)号:US11934098B2

    公开(公告)日:2024-03-19

    申请号:US18062100

    申请日:2022-12-06

    CPC classification number: G03F7/0002 G03F9/7069 G03F9/7084 G03F9/7088

    Abstract: The present invention provides a detection apparatus for detecting a position of a detection target including a diffraction grating pattern, comprising: an illuminator configured to illuminate the detection target with illumination light including a plurality of wavelengths; a wavelength selector including an incident surface on which diffracted light from the detection target is incident, and configured to select light of a specific wavelength from the diffracted light; and a detector configured to receive the light of the specific wavelength selected by the wavelength selector and detect the position of the detection target, wherein positions on the incident surface where light components of the plurality of wavelengths included in the illumination light are incident are different from each other, and wherein the wavelength selector controls each of the plurality of elements in accordance with the position on the incident surface.

    METHODS FOR FORMING ALIGNMENT MARKS
    9.
    发明公开

    公开(公告)号:US20240069448A1

    公开(公告)日:2024-02-29

    申请号:US17900124

    申请日:2022-08-31

    CPC classification number: G03F7/70633 G03F9/7088

    Abstract: A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.

    MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS

    公开(公告)号:US20240036486A1

    公开(公告)日:2024-02-01

    申请号:US18337028

    申请日:2023-06-18

    CPC classification number: G03F9/708 G03F9/7088 G03F9/7084

    Abstract: Provided is a manufacturing method of a semiconductor apparatus including: detecting a position by detecting positional deviation of the upper surface mark and the lower surface mark, by acquiring an upper surface image obtained by observing the upper surface mark from above the upper surface of the semiconductor substrate and a lower surface image obtained by observing the lower surface mark through the semiconductor substrate from above the upper surface of the semiconductor substrate; and forming an element by forming a semiconductor element in the semiconductor substrate, where in a top view in which the upper surface mark and the lower surface mark are projected onto a plane parallel to the upper surface, one of the upper surface mark and the lower surface mark is larger than an other, and the one entirely covers the other.

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