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    DATA ALIGNMENT CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS
    1.
    发明申请
    DATA ALIGNMENT CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS 有权
    数据对准电路和半导体存储器件的方法

    公开(公告)号：US20100329040A1

    公开(公告)日：2010-12-30

    申请号：US12649066

    申请日：2009-12-29

    申请人： Chun Seok JEONG ,  Kee Teok PARK ,  Chang Sik YOO ,  Jang Woo LEE ,  Hong Jung KIM

    发明人： Chun Seok JEONG ,  Kee Teok PARK ,  Chang Sik YOO ,  Jang Woo LEE ,  Hong Jung KIM

    IPC分类号： G11C7/10 ,  G11C7/00 ,  G11C8/18

    CPC分类号： G11C7/22 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222

    摘要： A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured to control phases of input data in response to data delay codes and generate delayed data; a plurality of data alignment blocks configured to latch the delayed data in response to the delayed strobe clock signal and generate latched data and aligned data; and a delay code generation block configured to perform an operation of determining phases of the latched data and generate the strobe delay code and the data delay codes.

    摘要翻译： 半导体存储装置的数据对准电路包括：数据选通时钟相位控制块，被配置为响应于选通延迟码来控制数据选通时钟信号的相位，并产生延迟的选通时钟信号; 多个数据相位控制块，被配置为响应于数据延迟码来控制输入数据的相位并产生延迟的数据; 多个数据对准块被配置为响应延迟的选通时钟信号来锁存延迟的数据，并产生锁存的数据和对准的数据; 以及延迟码生成块，被配置为执行确定所述锁存数据的相位的操作，并生成所述选通延迟码和所述数据延迟码。

    SEMICONDUCTOR APPARATUS WITH OPEN BIT LINE STRUCTURE
    2.
    发明申请
    SEMICONDUCTOR APPARATUS WITH OPEN BIT LINE STRUCTURE 有权
    具有开口线结构的半导体器件

    公开(公告)号：US20120218835A1

    公开(公告)日：2012-08-30

    申请号：US13339183

    申请日：2011-12-28

    申请人： Tae Sik YUN ,  Kee Teok PARK

    发明人： Tae Sik YUN ,  Kee Teok PARK

    IPC分类号： G11C7/06 ,  G11C7/00

    CPC分类号： G11C11/4099 ,  G11C11/401 ,  G11C29/24 ,  G11C2029/1202

    摘要： A semiconductor apparatus with an open bit line structure includes a memory bank including a plurality of memory cell blocks and dummy mats, in which a plurality of bit lines are formed, a bit line sense amplifier configured to be arranged between the plurality of memory cell blocks and the dummy mats, compare a voltage difference between a bit line and a complementary bit line, and amplify the difference, and a dummy word line driving unit configured to selectively activate a dummy word line of the dummy mat in response to a test mode.

    摘要翻译： 具有开放位线结构的半导体装置包括：存储体，其包括多个存储单元块和形成有多个位线的虚拟垫;配置为布置在多个存储单元块之间的位线读出放大器 和虚拟垫，比较位线和互补位线之间的电压差，并放大差值;虚拟字线驱动单元，被配置为响应于测试模式选择性地激活虚拟垫的虚拟字线。