公开(公告)号：US20120218835A1

公开(公告)日：2012-08-30

申请号：US13339183

申请日：2011-12-28

申请人： Tae Sik YUN ,  Kee Teok PARK

发明人： Tae Sik YUN ,  Kee Teok PARK

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C11/4099 ,  G11C11/401 ,  G11C29/24 ,  G11C2029/1202

摘要： A semiconductor apparatus with an open bit line structure includes a memory bank including a plurality of memory cell blocks and dummy mats, in which a plurality of bit lines are formed, a bit line sense amplifier configured to be arranged between the plurality of memory cell blocks and the dummy mats, compare a voltage difference between a bit line and a complementary bit line, and amplify the difference, and a dummy word line driving unit configured to selectively activate a dummy word line of the dummy mat in response to a test mode.

摘要翻译： 具有开放位线结构的半导体装置包括：存储体，其包括多个存储单元块和形成有多个位线的虚拟垫;配置为布置在多个存储单元块之间的位线读出放大器 和虚拟垫，比较位线和互补位线之间的电压差，并放大差值;虚拟字线驱动单元，被配置为响应于测试模式选择性地激活虚拟垫的虚拟字线。

公开(公告)号：US20130049833A1

公开(公告)日：2013-02-28

申请号：US13445761

申请日：2012-04-12

申请人： Sang Jin BYEON ,  Tae Sik YUN

发明人： Sang Jin BYEON ,  Tae Sik YUN

IPC分类号： H03L7/00 ,  H03K3/017

CPC分类号： H03K5/06 ,  G06F1/12 ,  H03K5/08

摘要： A semiconductor apparatus is provided. The apparatus includes a transmission control unit configured to generate, in response to a received pulse signal having a first pulse width, transmission control signals with a second pulse width larger than the first pulse width and synchronization control signals with a third pulse width larger than the second pulse width. The apparatus also includes a reception control unit configured to generate reception control signals in response to the synchronization control signals.

摘要翻译： 提供一种半导体装置。 该装置包括：传输控制单元，被配置为响应于具有第一脉冲宽度的接收脉冲信号，生成具有大于第一脉冲宽度的第二脉冲宽度的传输控制信号和具有大于第一脉冲宽度的第三脉冲宽度的同步控制信号 第二脉冲宽度。 该装置还包括：接收控制单元，被配置为响应于同步控制信号产生接收控制信号。

公开(公告)号：US20120119764A1

公开(公告)日：2012-05-17

申请号：US13181921

申请日：2011-07-13

申请人： Tae Sik YUN ,  Jong Chern LEE

发明人： Tae Sik YUN ,  Jong Chern LEE

IPC分类号： G01R31/00

CPC分类号： G01R31/31724 ,  G11C29/14 ,  G11C29/46 ,  G11C29/78 ,  G11C29/802

摘要： Various embodiments of a test mode control circuit of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, the test mode control circuit may include: a test mode control block configured to generate a plurality of control signal sets in response to a first address signal set and a second address signal set which are sequentially inputted; a test mode transfer block configured to transfer a plurality of test mode signals, which are generated according to a combination of the plurality of control signal sets, to a plurality of circuit blocks of the semiconductor apparatus; and a plurality of global lines configured to transmit the plurality of control signal sets to the test mode transfer block.

摘要翻译： 公开了半导体装置的测试模式控制电路的各种实施例及相关方法。 在一个示例性实施例中，测试模式控制电路可以包括：测试模式控制块，被配置为响应于顺序地输入的第一地址信号组和第二地址信号组而产生多个控制信号集; 测试模式传送块，被配置为将根据所述多个控制信号组的组合产生的多个测试模式信号传送到所述半导体装置的多个电路块; 以及配置成将多个控制信号组发送到测试模式传送块的多个全局线。

公开(公告)号：US20110025364A1

公开(公告)日：2011-02-03

申请号：US12637198

申请日：2009-12-14

申请人： Tae Sik YUN

发明人： Tae Sik YUN

IPC分类号： G01R31/26 ,  G06F11/00

CPC分类号： G01R31/31701

摘要： Various embodiments of a test mode signal generating device are disclosed. The device includes first and second test mode signal generating units. The first test mode signal generating unit is configured to receive test address signals to generate a first test mode signal when a first mode conversion signal is enabled. The first test mode signal generating unit is also configured to enable a second mode conversion signal when the test address signals correspond to a first predetermined combination. The second test mode signal generating unit is configured to receive the test address signals to generate a second test mode signal when the second mode conversion signal is enabled. The second test mode signal generating unit is also configured to enable the first mode conversion signal when the test address signals correspond to a second predetermined combination.

摘要翻译： 公开了测试模式信号产生装置的各种实施例。 该装置包括第一和第二测试模式信号发生单元。 第一测试模式信号产生单元被配置为当启用第一模式转换信号时接收测试地址信号以产生第一测试模式信号。 第一测试模式信号产生单元还被配置为当测试地址信号对应于第一预定组合时启用第二模式转换信号。 第二测试模式信号产生单元被配置为当第二模式转换信号被使能时，接收测试地址信号以产生第二测试模式信号。 第二测试模式信号产生单元还被配置为当测试地址信号对应于第二预定组合时使能第一模式转换信号。

公开(公告)号：US20130241314A1

公开(公告)日：2013-09-19

申请号：US13602257

申请日：2012-09-03

申请人： Tae Sik YUN ,  Sang Jin BYEON

发明人： Tae Sik YUN ,  Sang Jin BYEON

IPC分类号： H03K17/00

CPC分类号： H01L25/0657 ,  G01R31/2882 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H03K17/14 ,  H03K19/00369 ,  Y10T307/826

摘要： A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

摘要翻译： 半导体装置包括：从芯片，包括信号传送单元，配置为响应于芯片选择信号确定是否传送输入信号; 包括具有与信号传送单元相同配置的复制电路单元的主芯片和被配置为接收信号传送单元的输出信号和复制电路单元的输出信号的信号输出单元，并响应于 控制信号; 通过垂直形成的从芯片的第一通芯片，并且一端连接到主芯片以接收输入信号，另一端连接到信号传送单元; 以及通过垂直形成的从芯片的第二通芯片，并且其一端连接到信号传送单元，另一端连接到信号输出单元。

公开(公告)号：US20120057413A1

公开(公告)日：2012-03-08

申请号：US12948874

申请日：2010-11-18

申请人： Tae Sik YUN ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Jin Byeon ,  Sang Hoon Shin

发明人： Tae Sik YUN ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Jin Byeon ,  Sang Hoon Shin

IPC分类号： G11C8/18 ,  G11C29/00 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C29/006 ,  G11C29/023

摘要： A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.

摘要翻译： 一种半导体存储装置，包括：时钟控制单元，被配置为当使能信号被激活时接收第一时钟，并产生具有与第一时钟相对于目标时钟周期更长的周期的第二时钟; DLL输入时钟生成单元，被配置为根据DLL选择信号将第一时钟和第二时钟中的一个作为DLL输入时钟输出; 以及地址/命令输入时钟生成单元，被配置为根据使能信号将第一时钟和第二时钟中的一个作为AC输入时钟输出。

公开(公告)号：US20110232078A1

公开(公告)日：2011-09-29

申请号：US12839367

申请日：2010-07-19

申请人： Tae Sik YUN ,  Won Woong Seok

发明人： Tae Sik YUN ,  Won Woong Seok

IPC分类号： G01R31/28 ,  B23P21/00

CPC分类号： H01L22/14 ,  G01R31/318513 ,  H01L22/22 ,  Y10T29/49004 ,  Y10T29/53022 ,  Y10T29/53174 ,  Y10T29/53265

摘要： A semiconductor apparatus includes a semiconductor chip through-line for transmitting signals commonly to a plurality of stacked semiconductor chips. The apparatus includes a first test pulse signal transmission unit configured to transmit a first test pulse signal to a first end of the semiconductor chip through-line when a power-up operation is performed; a second test pulse signal transmission unit configured to transmit a second test pulse signal to a second end of the semiconductor chip through-line after the first test pulse signal is transmitted; a first signal reception unit coupled to the first end of the semiconductor chip through-line, and configured to receive signals transmitted from the first and second test pulse signal transmission units; and a second signal reception unit coupled to the second end of the semiconductor chip through-line, and configured to receive the signals transmitted by the first and second test pulse signal transmission units.

摘要翻译： 半导体装置包括用于将信号共同地传送到多个堆叠的半导体芯片的半导体芯片直通线。 该装置包括：第一测试脉冲信号发送单元，被配置为当执行上电操作时将第一测试脉冲信号发送到半导体芯片通过线的第一端; 第二测试脉冲信号发送单元，被配置为在发送所述第一测试脉冲信号之后将第二测试脉冲信号发送到所述半导体芯片直通线的第二端; 第一信号接收单元，耦合到半导体芯片通过线的第一端，并且被配置为接收从第一和第二测试脉冲信号传输单元发送的信号; 以及第二信号接收单元，其耦合到半导体芯片贯穿线的第二端，并且被配置为接收由第一和第二测试脉冲信号传输单元发送的信号。

公开(公告)号：US20110158015A1

公开(公告)日：2011-06-30

申请号：US12836526

申请日：2010-07-14

申请人： Tae Sik YUN ,  Won Woong SEOK

发明人： Tae Sik YUN ,  Won Woong SEOK

IPC分类号： G11C29/00

CPC分类号： G11C29/46

摘要： A test mode signal generation device includes a pulse address generation unit configured to convert test address signals into pulse signals and generate pulse address signals, a pulse address split unit configured to generate converted test address signals in response to the pulse address signals, and a test mode signal generation unit configured to generate a test mode signal in response to the converted test address signals.

摘要翻译： 测试模式信号产生装置包括：脉冲地址生成单元，被配置为将测试地址信号转换为脉冲信号并产生脉冲地址信号;脉冲地址分割单元，被配置为响应于脉冲地址信号生成转换的测试地址信号;以及测试 模式信号生成单元，被配置为响应于所转换的测试地址信号而生成测试模式信号。

公开(公告)号：US20120287699A1

公开(公告)日：2012-11-15

申请号：US13355781

申请日：2012-01-23

申请人： Tae Sik YUN ,  Kang Seol LEE

发明人： Tae Sik YUN ,  Kang Seol LEE

IPC分类号： G11C11/24 ,  G11C7/12 ,  G11C7/06

CPC分类号： G11C11/4076 ,  G11C11/4091 ,  G11C11/4099

摘要： A semiconductor memory device selects one of a plurality of memory cells as a dummy memory cell. The dummy memory cell is connected to a bit line that is complementary to a bit line connected to a selected memory cell. This technique advantageously compensates capacitance of the bit line. The semiconductor memory device comprises a selected memory cell connected to a first bit line and a first word line, a dummy memory cell connected to a second bit line complementary to the first bit line and a second word line, and a sense amplifier connected to the first and second bit lines and configured to read data stored in the selected memory cell by simultaneously enablement of the first and second word lines.

摘要翻译： 半导体存储器件选择多个存储单元中的一个作为虚拟存储单元。 虚拟存储器单元连接到与连接到所选存储单元的位线互补的位线。 该技术有利地补偿位线的电容。 半导体存储器件包括连接到第一位线和第一字线的选定存储器单元，连接到与第一位线互补的第二位线和第二字线的虚拟存储器单元，以及连接到第一位线的读出放大器 第一和第二位线，并且被配置为通过同时启用第一和第二字线来读取存储在所选存储单元中的数据。

公开(公告)号：US20120218843A1

公开(公告)日：2012-08-30

申请号：US13406117

申请日：2012-02-27

申请人： Tae Sik YUN ,  Kang Seol LEE

发明人： Tae Sik YUN ,  Kang Seol LEE

IPC分类号： G11C11/406 ,  G11C7/22

CPC分类号： G11C11/40618 ,  G11C29/783

摘要： Provided is a semiconductor device which performs a refresh operation by sequentially counting a refresh address including a main word line address, a mat address, and a sub word line address in order of the main word line address, the mat address, and the sub word line address. The semiconductor device includes a control signal generation unit configured to activate, latch, and output a toggle control signal when a delayed refresh signal is inputted at the initial stage, deactivate and output the toggle control signal after additionally counting a redundancy word line address when counting of the main word line address with respect to the mat address is completed, and then activate, latch, and output the toggle control signal when the delayed refresh signal is inputted.

摘要翻译： 提供一种半导体器件，其通过按照主字线地址，子地址和子字的顺序依次计数包括主字线地址，字地址和子字线地址的刷新地址来执行刷新操作 行地址。 该半导体装置包括：控制信号生成单元，被配置为当在初始阶段输入延迟的刷新信号时激活，锁存和输出触发控制信号，在对计数后的冗余字线地址进行额外计数之后停用并输出触发控制信号 完成相对于地址地址的主字线地址，然后当延迟刷新信号被输入时，激活，锁存和输出触发控制信号。