利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

69 条记录 (耗时 0.041 秒)

    Filter cut-off frequency correction circuit
    3.
    发明授权
    Filter cut-off frequency correction circuit 有权
    滤波器截止频率校正电路

    公开(公告)号：US08044710B2

    公开(公告)日：2011-10-25

    申请号：US12684876

    申请日：2010-01-08

    申请人： Sinn-Young Kim ,  Chang-Sik Yoo

    发明人： Sinn-Young Kim ,  Chang-Sik Yoo

    IPC分类号： H03K5/00

    CPC分类号： H03H11/1291 ,  H03H11/04

    摘要： A filter cut-off frequency correction circuit, inputted with a step function increasing from a first voltage to a second voltage, comprises a linear passive filter, for integrating the step function to obtain a third voltage; a first comparator, outputting a first high-level signal when the third voltage is greater than a first predetermined reference voltage; a second comparator, outputting a second high-level signal in a first period from the time that the second voltage is applied to the time that the first comparator outputs the first high-level signal; a counter, for counting a number of clock pulses of a reference clock inputted in the first period; a digital block, for calculating a variation rate of time constant according to the number of clock pulses of the reference clock, and generating a correction code; and a filter, for correcting the cut-off frequency according to the correction code. The correction circuit can improve the speed of cut-off frequency adjustment.

    摘要翻译： 输入从第一电压增加到第二电压的阶梯函数的滤波器截止频率校正电路包括线性无源滤波器，用于积分步长函数以获得第三电压; 第一比较器，当所述第三电压大于第一预定参考电压时，输出第一高电平信号; 第二比较器，从施加所述第二电压的时间到所述第一比较器输出所述第一高电平信号的时间的第一时段中输出第二高电平信号; 计数器，用于计数在第一周期中输入的参考时钟的数量的时钟脉冲; 数字块，用于根据参考时钟的时钟脉冲数来计算时间常数的变化率，并产生校正码; 以及滤波器，用于根据校正码校正截止频率。 校正电路可以提高截止频率调节的速度。

    Integrated circuit memory devices including mode registers set using a data input/output bus
    4.
    发明授权
    Integrated circuit memory devices including mode registers set using a data input/output bus 有权
    集成电路存储器件包括使用数据输入/输出总线设置的模式寄存器

    公开(公告)号：US07804720B2

    公开(公告)日：2010-09-28

    申请号：US12614826

    申请日：2009-11-09

    申请人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

    发明人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

    IPC分类号： G11C7/10

    CPC分类号： G11C5/00 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/222 ,  G11C8/06 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4093

    摘要： An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed.

    摘要翻译： 集成电路存储器件可以包括存储单元阵列和多个数据输入/输出引脚。 多个数据输入/输出引脚可以被配置为在数据写入操作期间从存储器控制器接收要写入存储单元阵列的数据，并且数据输入/输出引脚还可以被配置为向存储器控制器 在数据读取操作期间从存储单元阵列。 模式寄存器可以被配置为存储定义存储器件的操作特性的信息，并且模式寄存器可以被配置为使用数据输入/输出总线进行设置。 还讨论了相关方法，系统和附加设备。

    Integrated circuit memory devices that support selective mode register set commands
    5.
    发明授权
    Integrated circuit memory devices that support selective mode register set commands 有权
    支持选择性模式寄存器设置命令的集成电路存储器件

    公开(公告)号：US07636273B2

    公开(公告)日：2009-12-22

    申请号：US12260373

    申请日：2008-10-29

    申请人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

    发明人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

    IPC分类号： G11C8/00

    CPC分类号： G11C5/00 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/222 ,  G11C8/06 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4093

    摘要： A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed.

    摘要翻译： 存储器模块可以包括通过相同的命令/地址总线耦合到存储器控制器的多个存储器件。 控制这种存储器模块的方法可以包括在模式寄存器设置操作期间通过命令/地址总线从存储器控制器向每个集成电路存储器件提供模式寄存器设置命令。 可以通过存储器控制器和第一集成电路存储器件之间的信号线从存储器控制器向集成电路存储器件中的第一个提供禁止信号，从而禁止第一集成电路的模式寄存器设置命令的实现 存储器件在模式寄存器设置操作期间。 可以通过存储器控制器和第二集成电路存储器件之间的信号线从存储器控制器向集成电路存储器件中的第二个提供使能信号，从而能够实现第二集成电路的模式寄存器设置命令 存储器件在模式寄存器设置操作期间。 此外，在模式寄存器设置操作期间，禁止信号可能不被提供给第二集成电路存储器件，并且在模式寄存器设置操作期间可以不向第一集成电路存储器件提供使能信号。 还讨论了相关系统，设备和附加方法。

    Data output circuit and method in DDR synchronous semiconductor device
    6.
    发明授权
    Data output circuit and method in DDR synchronous semiconductor device 有权
    DDR同步半导体器件数据输出电路及方法

    公开(公告)号：US07558127B2

    公开(公告)日：2009-07-07

    申请号：US12105209

    申请日：2008-04-17

    申请人： Nak-Won Heo ,  Chang-Sik Yoo

    发明人： Nak-Won Heo ,  Chang-Sik Yoo

    IPC分类号： G11C7/00 ,  G11C11/34 ,  G06F12/00 ,  G06F13/00

    CPC分类号： G11C7/1066 ,  G11C7/1039 ,  G11C7/1051 ,  G11C2207/107

    摘要： Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

    摘要翻译： 本发明的实施例包括可以从流水线电路中的多个锁存器并行读取数据的数据输出电路。 偶数数据和奇数数据同时在单个时钟周期输出，然后被转换成DDR数据，然后被串行输出。 通过以这种方式移动数据，与常规数据输出电路相比，本发明的实施例可以将所需控制信号的数量减少多达50％。

    Methods of Operating Memory Systems Including Memory Devices Set to Different Operating Modes
    7.
    发明申请
    Methods of Operating Memory Systems Including Memory Devices Set to Different Operating Modes 审中-公开
    操作内存系统的方法，包括设置为不同操作模式的内存设备

    公开(公告)号：US20080175071A1

    公开(公告)日：2008-07-24

    申请号：US12058441

    申请日：2008-03-28

    申请人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

    发明人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

    IPC分类号： G11C7/10 ,  G11C8/00

    CPC分类号： G06F13/1694 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/4093

    摘要： A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.

    摘要翻译： 可以提供一种操作包括耦合到命令地址总线的多个存储器件的存储器系统的方法。 特别地，多个存储器件的第一存储器件可以被设置为第一操作模式，并且多个存储器件中的第二存储器件可以被设置为与第一操作模式不同的第二操作模式。 此外，可以响应于通过命令地址总线提供给多个存储器件的读/写命令地址信号执行读/写操作，使得第一存储器件在读/写期间根据第一操作模式进行操作 并且使得第二存储器件在读/写操作期间根据第二操作模式操作。 还讨论了相关系统。

    Data output circuit and method in DDR synchronous semiconductor device
    8.
    发明授权
    Data output circuit and method in DDR synchronous semiconductor device 有权
    DDR同步半导体器件数据输出电路及方法

    公开(公告)号：US07376021B2

    公开(公告)日：2008-05-20

    申请号：US10411724

    申请日：2003-04-11

    申请人： Nak-Won Heo ,  Chang-Sik Yoo

    发明人： Nak-Won Heo ,  Chang-Sik Yoo

    IPC分类号： G11C7/00 ,  G11C11/34 ,  G06F12/00 ,  G06F13/00

    CPC分类号： G11C7/1066 ,  G11C7/1039 ,  G11C7/1051 ,  G11C2207/107

    摘要： Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

    摘要翻译： 本发明的实施例包括可以从流水线电路中的多个锁存器并行读取数据的数据输出电路。 偶数数据和奇数数据同时在单个时钟周期输出，然后被转换成DDR数据，然后被串行输出。 通过以这种方式移动数据，与常规数据输出电路相比，本发明的实施例可以将所需控制信号的数量减少多达50％。

    Open-loop digital duty cycle correction circuit without DLL
    10.
    发明授权
    Open-loop digital duty cycle correction circuit without DLL 有权
    开环数字占空比校正电路，无DLL

    公开(公告)号：US07212055B2

    公开(公告)日：2007-05-01

    申请号：US10876402

    申请日：2004-06-24

    申请人： Chang-Sik Yoo ,  Chun-Seok Jeong

    发明人： Chang-Sik Yoo ,  Chun-Seok Jeong

    IPC分类号： H03K3/017

    CPC分类号： H03K5/135 ,  H03K5/15066 ,  H03K5/1565

    摘要： The present invention relates to a semiconductor circuit; and, more particularly, to a duty cycle correction circuit (hereinafter referred to as “DCC”). Furthermore, the present invention relates to an open-loop digital DCC. The duty cycle correction circuit according to the present invention includes: a delayer for delaying an input clock signal and for generating a plurality of delayed clock; a phase comparator for comparing the input clock signal with the plurality of delayed clock signals; a multiplexer for selecting one out of the delayed clock signals in response to an output signal of the phase comparator and for inverting the selected delay clock signals; and a phase combiner for combining the clock signal from the multiplexer and the input clock signal. Accordingly, the digital DCC according to the present invention is of an open loop without any DLL, the duty correction can be made within five clock periods after power-up.

    摘要翻译： 本发明涉及半导体电路; 更具体地说，涉及占空比校正电路（以下称为“DCC”）。 此外，本发明涉及开环数字DCC。 根据本发明的占空比校正电路包括：延迟器，用于延迟输入时钟信号并产生多个延迟时钟; 相位比较器，用于将输入时钟信号与多个延迟的时钟信号进行比较; 多路复用器，用于响应于相位比较器的输出信号选择延迟时钟信号中的一个并用于反相所选择的延迟时钟信号; 以及用于组合来自多路复用器的时钟信号和输入时钟信号的相位组合器。 因此，根据本发明的数字DCC是没有任何DLL的开环，可以在上电之后的五个时钟周期内进行占空比校正。