公开(公告)号：US07342991B2

公开(公告)日：2008-03-11

申请号：US11385544

申请日：2006-03-20

申请人： Chun-Ching Wei ,  Yang-En Wu ,  Wei-Cheng Lin

发明人： Chun-Ching Wei ,  Yang-En Wu ,  Wei-Cheng Lin

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G11C19/00

摘要： A shift register without a feedback signal of a post-stage shift register utilizing a latch mechanism and a clock signal to control the voltage of an output of the shift register is provided. The shift register reduces the transistor size and the circuit layout area. The shift register also improves the issue the overlapping between two adjacent shift registers to reduce the after-image of a liquid crystal display.

摘要翻译： 提供了没有使用锁存机构的后级移位寄存器的反馈信号的移位寄存器和用于控制移位寄存器的输出的电压的时钟信号。 移位寄存器可以减小晶体管尺寸和电路布局面积。 移位寄存器还改善了两个相邻移位寄存器之间的重叠以减少液晶显示器的后置图像的问题。

公开(公告)号：US20070188436A1

公开(公告)日：2007-08-16

申请号：US11456561

申请日：2006-07-10

申请人： Chun-Ching Wei ,  Wei-Cheng Lin ,  Shih-Hsun Lo ,  Yang-En Wu

发明人： Chun-Ching Wei ,  Wei-Cheng Lin ,  Shih-Hsun Lo ,  Yang-En Wu

IPC分类号： G09G3/36

CPC分类号： G11C19/00 ,  G09G3/3677

摘要： A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register in response to a clock signal while the signal generating circuit is turned on, a driving circuit electrically coupled to the signal generating circuit for controlling the signal generating circuit in response to an input signal received from an input end of the shift register, a primary reset circuit electrically coupled to the signal generating circuit for turning off the signal generating circuit and resetting the output signal from the output end, and a feedback circuit electrically coupled to the output end and the major reset circuit for controlling the primary reset circuit in response to the output signal and the clock signal.

摘要翻译： 移位寄存器包括：信号发生电路，用于在信号产生电路导通时响应于时钟信号在移位寄存器的输出端产生输出信号;驱动电路，电耦合到信号发生电路，用于控制信号 响应于从所述移位寄存器的输入端接收到的输入信号产生电路;电耦合到所述信号发生电路的主复位电路，用于关闭所述信号发生电路并且从所述输出端复位所述输出信号;以及反馈电路 电耦合到输出端和主复位电路，用于响应于输出信号和时钟信号控制主复位电路。

公开(公告)号：US20070035505A1

公开(公告)日：2007-02-15

申请号：US11362213

申请日：2006-02-24

申请人： Wei-Cheng Lin ,  Chun-Ching Wei ,  Yang-En Wu ,  Cheng-Liang Ma

发明人： Wei-Cheng Lin ,  Chun-Ching Wei ,  Yang-En Wu ,  Cheng-Liang Ma

IPC分类号： G09G3/36

CPC分类号： G11C19/28 ,  G09G3/3648 ,  G09G2310/0286 ,  G09G2320/0219

摘要： A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down module coupling to the output, output signals of pre-stage and post-stage shift register, a second and a third voltage level. When the second transistor turns on and the first clock signal is at high voltage level, the output is at a first voltage level. When the signal of post-stage shift register is at first voltage level, the output is at the third voltage level.

摘要翻译： 具有一系列级联移位寄存器的移位寄存器电路包括耦合到前级移位寄存器的输出信号的第一晶体管，耦合到第一晶体管的第二晶体管，输出和第一时钟信号以及下拉 模块耦合到输出，前级和后级移位寄存器的输出信号，第二和第三电压电平。 当第二晶体管导通并且第一时钟信号处于高电压电平时，输出处于第一电压电平。 当后级移位寄存器的信号处于第一电压电平时，输出处于第三电压电平。

公开(公告)号：US20070086558A1

公开(公告)日：2007-04-19

申请号：US11302853

申请日：2005-12-13

申请人： Chun-Ching Wei ,  Yang-En Wu ,  Wei-Cheng Lin

发明人： Chun-Ching Wei ,  Yang-En Wu ,  Wei-Cheng Lin

IPC分类号： G11C19/00

CPC分类号： G11C19/28

摘要： A shift register in an amorphous-silicon gate driver comprises a pull-up transistor and two pull-down modules. The pull-up transistor produces a positive pulse when the clock signal is high and the gate of the pull-up transistor is also high. The gate of the pull-up transistor is pulled down to a negative voltage level Vss by two pull-down transistors in the pull-down modules. Each pull-down module also has a further pull-down transistor to keep the output terminal at Vss after the output pulse is produced. The two pull-down modules are operated in a cooperative manner so that each pull-down transistor is conducting approximately 50% of the time. The gates of the pull-down transistors are kept at a positive voltage level approximately 50% of the time and at Vss′ approximately 50% of the time with Vss′ being more negative than Vss.

公开(公告)号：US07636077B2

公开(公告)日：2009-12-22

申请号：US11302917

申请日：2005-12-13

申请人： Chun-Ching Wei ,  Yang-En Wu ,  Wei-Cheng Lin

发明人： Chun-Ching Wei ,  Yang-En Wu ,  Wei-Cheng Lin

IPC分类号： G09G3/36

CPC分类号： G02F1/1345 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2330/08 ,  G11C19/287 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A backup shift register module having at least two backup shift registers is used to repair a defective main shift-register module. A normally open link is provided between the input of first backup shift register and the input of each odd-numbered main shift register, and between the output of first backup shift register and the input of each even-numbered main shift register. A normally open link is provided between the input of second backup shift register and the input of each even-numbered main shift register, and between the output of second backup shift register and the input of each odd-numbered main shift register. If one main shift register is defective, the input and output of the defective shift register are disconnected from the cascade link, and the normally open links are connected to the input of the defective shift register and the output of the next shift register are connected.

摘要翻译： 具有至少两个备用移位寄存器的备用移位寄存器模块用于修复有缺陷的主移位寄存器模块。 在第一备用移位寄存器的输入和每个奇数主移位寄存器的输入之间以及第一备用移位寄存器的输出和每个偶数主移位寄存器的输入之间提供常开链路。 在第二备用移位寄存器的输入和每个偶数主移位寄存器的输入之间以及第二备用移位寄存器的输出和每个奇数主移位寄存器的输入之间提供常开链路。 如果一个主移位寄存器有故障，则有缺陷移位寄存器的输入和输出与级联链路断开，而常开链路连接到有缺陷的移位寄存器的输入端，下一个移位寄存器的输出端连接。

公开(公告)号：US07450681B2

公开(公告)日：2008-11-11

申请号：US11456561

申请日：2006-07-10

申请人： Chun-Ching Wei ,  Wei-Cheng Lin ,  Shih-Hsun Lo ,  Yang-En Wu

发明人： Chun-Ching Wei ,  Wei-Cheng Lin ,  Shih-Hsun Lo ,  Yang-En Wu

IPC分类号： H03K5/22

CPC分类号： G11C19/00 ,  G09G3/3677

摘要： A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register in response to a clock signal while the signal generating circuit is turned on, a driving circuit electrically coupled to the signal generating circuit for controlling the signal generating circuit in response to an input signal received from an input end of the shift register, a primary reset circuit electrically coupled to the signal generating circuit for turning off the signal generating circuit and resetting the output signal from the output end, and a feedback circuit electrically coupled to the output end and the major reset circuit for controlling the primary reset circuit in response to the output signal and the clock signal.

摘要翻译： 移位寄存器包括：信号发生电路，用于在信号产生电路导通时响应于时钟信号在移位寄存器的输出端产生输出信号;驱动电路，电耦合到信号发生电路，用于控制信号 响应于从所述移位寄存器的输入端接收到的输入信号产生电路;电耦合到所述信号发生电路的主复位电路，用于关闭所述信号发生电路并且从所述输出端复位所述输出信号;以及反馈电路 电耦合到输出端和主复位电路，用于响应于输出信号和时钟信号控制主复位电路。

公开(公告)号：US07317780B2

公开(公告)日：2008-01-08

申请号：US11362213

申请日：2006-02-24

申请人： Wei-Cheng Lin ,  Chun-Ching Wei ,  Yang-En Wu ,  Cheng-Liang Ma

发明人： Wei-Cheng Lin ,  Chun-Ching Wei ,  Yang-En Wu ,  Cheng-Liang Ma

IPC分类号： G11K19/00 ,  H03K19/00

CPC分类号： G11C19/28 ,  G09G3/3648 ,  G09G2310/0286 ,  G09G2320/0219

摘要： A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down module coupling to the output, output signals of pre-stage and post-stage shift register, a second and a third voltage level. When the second transistor turns on and the first clock signal is at high voltage level, the output is at a first voltage level. When the signal of post-stage shift register is at first voltage level, the output is at the third voltage level.

摘要翻译： 具有一系列级联移位寄存器的移位寄存器电路包括耦合到前级移位寄存器的输出信号的第一晶体管，耦合到第一晶体管的第二晶体管，输出和第一时钟信号以及下拉 模块耦合到输出，前级和后级移位寄存器的输出信号，第二和第三电压电平。 当第二晶体管导通并且第一时钟信号处于高电压电平时，输出处于第一电压电平。 当后级移位寄存器的信号处于第一电压电平时，输出处于第三电压电平。

公开(公告)号：US20070046327A1

公开(公告)日：2007-03-01

申请号：US11385369

申请日：2006-03-21

申请人： Chun-Ching Wei ,  Yang-En Wu ,  Wei-Cheng Lin

发明人： Chun-Ching Wei ,  Yang-En Wu ,  Wei-Cheng Lin

IPC分类号： H03K19/173

CPC分类号： G11C19/28

摘要： A shift register circuit having shift registers comprising a first transistor having a gate and a first source/drain for receiving an output signal of a pre-stage shift register, a second transistor having a gate coupled to a second source/drain of the first transistor, a first source/drain coupled to a first clock signal, and a second source/drain coupled to a output, a first pull-down module coupled to the output terminal, for receiving the first clock signal, wherein the output is coupled to a first voltage level when the output signal of pre-stage shift register and the first clock signal are at low voltage level, and a second pull-down module coupled to the output and a second clock signal, wherein the output is coupled to a first voltage level when the output signal of pre-stage shift register and the second clock signal are at low voltage level.

摘要翻译： 一种移位寄存器电路，具有移位寄存器，该移位寄存器包括具有栅极的第一晶体管和用于接收前级移位寄存器的输出信号的第一源极/漏极;第二晶体管，其栅极耦合到第一晶体管的第二源极/漏极 耦合到第一时钟信号的第一源极/漏极和耦合到输出端的第二源极/漏极耦合到输出端子的第一下拉模块，用于接收第一时钟信号，其中输出耦合到 当前级移位寄存器和第一时钟信号的输出信号处于低电压电平时的第一电压电平，以及耦合到输出的第二下拉模块和第二时钟信号，其中输出耦合到第一电压 当前级移位寄存器和第二个时钟信号的输出信号处于低电平时，电平。

公开(公告)号：US20080143666A1

公开(公告)日：2008-06-19

申请号：US11754353

申请日：2007-05-28

申请人： Chun-Ching Wei ,  Wei-Cheng Lin ,  Shih-Hsun Lo ,  Yang-En Wu

发明人： Chun-Ching Wei ,  Wei-Cheng Lin ,  Shih-Hsun Lo ,  Yang-En Wu

IPC分类号： G11C19/00 ,  G09G3/36

CPC分类号： G11C19/28

摘要： A shift register includes a signal generating circuit, a driving circuit, a reset circuit, and a control switch. The signal generating circuit includes a first switch for generating a first output signal according to a clock signal while the first switch is turned on, and a second switch coupled to an output end of the shift register for generating and transmitting a second output signal to the output end of the shift register according to the clock signal while the second switch is turned on. The driving circuit is for controlling the first and second switches according to an input signal received from an input end of the shift register. The reset circuit is for turning off the first and second switches and resetting the output signal outputted by the output end. The control switch is for resetting the output signal outputted by the output end.

摘要翻译： 移位寄存器包括信号发生电路，驱动电路，复位电路和控制开关。 信号发生电路包括第一开关，用于在第一开关导通时根据时钟信号产生第一输出信号;以及第二开关，耦合到移位寄存器的输出端，用于产生和发送第二输出信号到 在第二开关导通时根据时钟信号输出移位寄存器的输出端。 驱动电路用于根据从移位寄存器的输入端接收的输入信号来控制第一和第二开关。 复位电路用于关闭第一和第二开关并复位由输出端输出的输出信号。 控制开关用于复位由输出端输出的输出信号。

公开(公告)号：US07342568B2

公开(公告)日：2008-03-11

申请号：US11385369

申请日：2006-03-21

申请人： Chun-Ching Wei ,  Yang-En Wu ,  Wei-Cheng Lin

发明人： Chun-Ching Wei ,  Yang-En Wu ,  Wei-Cheng Lin

IPC分类号： G09G3/36 ,  H03K19/096

CPC分类号： G11C19/28

摘要： A shift register circuit having shift registers comprising a first transistor having a gate and a first source/drain for receiving an output signal of a pre-stage shift register, a second transistor having a gate coupled to a second source/drain of the first transistor, a first source/drain coupled to a first clock signal, and a second source/drain coupled to a output, a first pull-down module coupled to the output terminal, for receiving the first clock signal, wherein the output is coupled to a first voltage level when the output signal of pre-stage shift register and the first clock signal are at low voltage level, and a second pull-down module coupled to the output and a second clock signal, wherein the output is coupled to a first voltage level when the output signal of pre-stage shift register and the second clock signal are at low voltage level.

摘要翻译： 一种移位寄存器电路，具有移位寄存器，该移位寄存器包括具有栅极的第一晶体管和用于接收前级移位寄存器的输出信号的第一源极/漏极;第二晶体管，其栅极耦合到第一晶体管的第二源极/漏极 耦合到第一时钟信号的第一源极/漏极和耦合到输出端的第二源极/漏极耦合到输出端子的第一下拉模块，用于接收第一时钟信号，其中输出耦合到 当前级移位寄存器和第一时钟信号的输出信号处于低电压电平时的第一电压电平，以及耦合到输出的第二下拉模块和第二时钟信号，其中输出耦合到第一电压 当前级移位寄存器和第二个时钟信号的输出信号处于低电平时，电平。