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公开(公告)号:US08729634B2
公开(公告)日:2014-05-20
申请号:US13525050
申请日:2012-06-15
申请人: Chun-Liang Shen , Kuo-Ching Tsai , Hou-Ju Li , Chun-Sheng Liang , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
发明人: Chun-Liang Shen , Kuo-Ching Tsai , Hou-Ju Li , Chun-Sheng Liang , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
IPC分类号: H01L21/762 , H01L29/06
CPC分类号: H01L29/1054 , H01L29/66818 , H01L29/7853 , H01L29/7854
摘要: An integrated circuit device includes a fin at least partially embedded in a shallow trench isolation (STI) region and extending between a source and a drain. The fin is formed from a first semiconductor material and having a trimmed portion between first and second end portions. A cap layer, which is formed from a second semiconductor material, is disposed over the trimmed portion of the fin to form a high mobility channel. A gate electrode structure is formed over the high mobility channel and between the first and second end portions.
摘要翻译: 集成电路器件包括至少部分地嵌入在浅沟槽隔离(STI)区域中并且在源极和漏极之间延伸的翅片。 翅片由第一半导体材料形成,并且在第一和第二端部之间具有修剪部分。 由第二半导体材料形成的盖层设置在翅片的修剪部分之上以形成高迁移率通道。 栅电极结构形成在高迁移率通道上,并在第一和第二端部之间。
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公开(公告)号:US20130334606A1
公开(公告)日:2013-12-19
申请号:US13525050
申请日:2012-06-15
申请人: Chun-Liang Shen , Kuo-Ching Tsai , Hou-Ju Li , Chun-Sheng Liang , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
发明人: Chun-Liang Shen , Kuo-Ching Tsai , Hou-Ju Li , Chun-Sheng Liang , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
IPC分类号: H01L29/78 , H01L21/336
CPC分类号: H01L29/1054 , H01L29/66818 , H01L29/7853 , H01L29/7854
摘要: An integrated circuit device includes a fin at least partially embedded in a shallow trench isolation (STI) region and extending between a source and a drain. The fin is formed from a first semiconductor material and having a trimmed portion between first and second end portions. A cap layer, which is formed from a second semiconductor material, is disposed over the trimmed portion of the fin to form a high mobility channel. A gate electrode structure is formed over the high mobility channel and between the first and second end portions.
摘要翻译: 集成电路器件包括至少部分地嵌入在浅沟槽隔离(STI)区域中并且在源极和漏极之间延伸的翅片。 翅片由第一半导体材料形成,并且在第一和第二端部之间具有修剪部分。 由第二半导体材料形成的盖层设置在翅片的修剪部分之上以形成高迁移率通道。 栅电极结构形成在高迁移率通道上,并在第一和第二端部之间。
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公开(公告)号:US09368628B2
公开(公告)日:2016-06-14
申请号:US13542468
申请日:2012-07-05
申请人: Hou-Ju Li , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
发明人: Hou-Ju Li , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
CPC分类号: H01L29/7848 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/66636 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要: An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.
摘要翻译: 集成电路器件包括鳍状物,栅极电极结构下方具有栅极区域,设置在鳍状物的末端以外的源极/漏极区域以及围绕源极/漏极区域的嵌入部分形成的第一共形层。 第一共形层的垂直侧壁平行于栅极区域定向。
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公开(公告)号:US20140008736A1
公开(公告)日:2014-01-09
申请号:US13542468
申请日:2012-07-05
申请人: Hou-Ju Li , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
发明人: Hou-Ju Li , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
IPC分类号: H01L29/78 , H01L21/336
CPC分类号: H01L29/7848 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/66636 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要: An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.
摘要翻译: 集成电路器件包括鳍状物,栅极电极结构下方具有栅极区域,设置在鳍状物的末端以外的源极/漏极区域以及围绕源极/漏极区域的嵌入部分形成的第一共形层。 第一共形层的垂直侧壁平行于栅极区域定向。
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公开(公告)号:US20110079820A1
公开(公告)日:2011-04-07
申请号:US12572743
申请日:2009-10-02
申请人: Kao-Ting Lai , Da-Wen Lin , Hsien-Hsin Lin , Yuan-Ching Peng , Chi-Hsi Wu
发明人: Kao-Ting Lai , Da-Wen Lin , Hsien-Hsin Lin , Yuan-Ching Peng , Chi-Hsi Wu
IPC分类号: H01L29/165 , H01L21/30 , H01L29/78
CPC分类号: H01L21/3247 , H01L29/66636 , H01L29/7848
摘要: A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.
摘要翻译: 一种方法包括提供包括衬底材料的衬底,在衬底上方的栅极电介质膜和与栅极电介质膜相邻的第一间隔物。 间隔物具有与基底的表面接触的第一部分和与栅极电介质膜的一侧接触的第二部分。 在与衬垫相邻的衬底的区域中形成凹部。 凹部由基底材料的第一侧壁限定。 第一侧壁的至少一部分位于间隔件的至少一部分的下面。 衬垫材料位于衬垫的第一部分下面被回流,使得限定凹陷的衬底材料的第一侧壁的顶部基本上与栅极电介质膜和间隔物之间的边界对齐。 凹陷部分填充有压力源材料。
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公开(公告)号:US08404538B2
公开(公告)日:2013-03-26
申请号:US12572743
申请日:2009-10-02
申请人: Kao-Ting Lai , Da-Wen Lin , Hsien-Hsin Lin , Yuan-Ching Peng , Chi-Hsi Wu
发明人: Kao-Ting Lai , Da-Wen Lin , Hsien-Hsin Lin , Yuan-Ching Peng , Chi-Hsi Wu
IPC分类号: H01L21/8238
CPC分类号: H01L21/3247 , H01L29/66636 , H01L29/7848
摘要: A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.
摘要翻译: 一种方法包括提供包括衬底材料的衬底,在衬底上方的栅极电介质膜和与栅极电介质膜相邻的第一间隔物。 间隔物具有与基底的表面接触的第一部分和与栅极电介质膜的一侧接触的第二部分。 在与衬垫相邻的衬底的区域中形成凹部。 凹部由基底材料的第一侧壁限定。 第一侧壁的至少一部分位于间隔件的至少一部分的下面。 衬垫材料位于衬垫的第一部分下面被回流,使得限定凹陷的衬底材料的第一侧壁的顶部基本上与栅极电介质膜和间隔物之间的边界对齐。 凹陷部分填充有压力源材料。
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