公开(公告)号：US08685853B2

公开(公告)日：2014-04-01

申请号：US13093809

申请日：2011-04-25

申请人： Fan Chung Tseng ,  Chi Hsi Wu ,  Wei Ting Chien

发明人： Fan Chung Tseng ,  Chi Hsi Wu ,  Wei Ting Chien

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807 ,  G03F1/50 ,  G03F1/54 ,  H01L2221/1021

摘要： A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two lithography steps: one to mask and expose the via, and a second step to mask and expose the trench interconnection. The novel method for creating a dual damascene structure allows for a smaller number of processing steps, thus reducing the processing time needed to complete the dual damascene structure. In addition, a lower number of masks may be needed. The exemplary mask or reticle used within the process incorporates different regions possessing different transmission rates. During the exposing step, light from an exposing source passes through the mask to expose a portion of the photoresist layer on top of the wafer. Depending on the transmission rate of the different regions, different thickness of the photoresist layer are exposed and later removed by a developing solution, which allows a subsequent etch process to remove portions of both the dielectric layer and photoresist layer to create a dual damascene structure.

摘要翻译： 一种用于仅使用一个光刻和掩蔽步骤来创建双镶嵌结构的方法。 传统的双镶嵌结构使用两个光刻步骤：一个用于掩蔽和暴露通孔，以及第二步骤，以掩蔽和暴露沟槽互连。 用于创建双镶嵌结构的新颖方法允许较少数量的处理步骤，从而减少完成双镶嵌结构所需的处理时间。 此外，可能需要较少数量的掩模。 在该过程中使用的示例性掩模或掩模版包含具有不同透射率的不同区域。 在曝光步骤期间，来自曝光源的光穿过掩模以暴露晶片顶部上的光致抗蚀剂层的一部分。 取决于不同区域的透射率，曝光不同厚度的光致抗蚀剂层，随后通过显影液去除，这使得随后的蚀刻工艺能够去除介电层和光致抗蚀剂层的部分以产生双镶嵌结构。

公开(公告)号：US07989341B2

公开(公告)日：2011-08-02

申请号：US11539614

申请日：2006-10-06

申请人： Fan Chung Tseng ,  Chi Hsi Wu ,  Wei Ting Chien

发明人： Fan Chung Tseng ,  Chi Hsi Wu ,  Wei Ting Chien

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807 ,  G03F1/50 ,  G03F1/54 ,  H01L2221/1021

摘要： A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two lithography steps: one to mask and expose the via, and a second step to mask and expose the trench interconnection. The novel method for creating a dual damascene structure allows for a smaller number of processing steps, thus reducing the processing time needed to complete the dual damascene structure. In addition, a lower number of masks may be needed. The exemplary mask or reticle used within the process incorporates different regions possessing different transmission rates. During the exposing step, light from an exposing source passes through the mask to expose a portion of the photoresist layer on top of the wafer. Depending on the transmission rate of the different regions, different thickness of the photoresist layer are exposed and later removed by a developing solution, which allows a subsequent etch process to remove portions of both the dielectric layer and photoresist layer to create a dual damascene structure.

摘要翻译： 一种用于仅使用一个光刻和掩蔽步骤来创建双镶嵌结构的方法。 传统的双镶嵌结构使用两个光刻步骤：一个用于掩蔽和暴露通孔，以及第二步骤，以掩蔽和暴露沟槽互连。 用于创建双镶嵌结构的新颖方法允许较少数量的处理步骤，从而减少完成双镶嵌结构所需的处理时间。 此外，可能需要较少数量的掩模。 在该过程中使用的示例性掩模或掩模版包含具有不同透射率的不同区域。 在曝光步骤期间，来自曝光源的光穿过掩模以暴露晶片顶部上的光致抗蚀剂层的一部分。 取决于不同区域的透射率，曝光不同厚度的光致抗蚀剂层，随后通过显影液去除，这使得随后的蚀刻工艺能够去除介电层和光致抗蚀剂层的部分以产生双镶嵌结构。

公开(公告)号：US20110079820A1

公开(公告)日：2011-04-07

申请号：US12572743

申请日：2009-10-02

申请人： Kao-Ting Lai ,  Da-Wen Lin ,  Hsien-Hsin Lin ,  Yuan-Ching Peng ,  Chi-Hsi Wu

发明人： Kao-Ting Lai ,  Da-Wen Lin ,  Hsien-Hsin Lin ,  Yuan-Ching Peng ,  Chi-Hsi Wu

IPC分类号： H01L29/165 ,  H01L21/30 ,  H01L29/78

CPC分类号： H01L21/3247 ,  H01L29/66636 ,  H01L29/7848

摘要： A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.

摘要翻译： 一种方法包括提供包括衬底材料的衬底，在衬底上方的栅极电介质膜和与栅极电介质膜相邻的第一间隔物。 间隔物具有与基底的表面接触的第一部分和与栅极电介质膜的一侧接触的第二部分。 在与衬垫相邻的衬底的区域中形成凹部。 凹部由基底材料的第一侧壁限定。 第一侧壁的至少一部分位于间隔件的至少一部分的下面。 衬垫材料位于衬垫的第一部分下面被回流，使得限定凹陷的衬底材料的第一侧壁的顶部基本上与栅极电介质膜和间隔物之间​​的边界对齐。 凹陷部分填充有压力源材料。

公开(公告)号：US07067359B2

公开(公告)日：2006-06-27

申请号：US10811405

申请日：2004-03-26

申请人： Chi-Hsi Wu

发明人： Chi-Hsi Wu

IPC分类号： H01L21/82 ,  H01L27/10

CPC分类号： H01L23/5256 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/13 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for providing an electrical fuse is provided. An electrical fuse is patterned from the active layer of a semiconductor-on-insulator (SOI) wafer. One shape of the electrical fuse may be a first and second portion electrically coupled via a third section. The third section is typically thinner than the first and second portion. An ion implant is performed to fully deplete the electrical fuse, and a silicidation process is performed. Thereafter, standard processing techniques may be used to form vias and other integrated circuit structures.

摘要翻译： 提供一种用于提供电熔丝的方法和装置。 从绝缘体上半导体（SOI）晶片的有源层图案化电熔丝。 电熔丝的一种形状可以是经由第三部分电耦合的第一和第二部分。 第三部分通常比第一和第二部分薄。 执行离子注入以完全耗尽电熔丝，并进行硅化处理。 此后，可以使用标准处理技术来形成通孔和其他集成电路结构。

公开(公告)号：US20120108054A1

公开(公告)日：2012-05-03

申请号：US13093809

申请日：2011-04-25

申请人： Fan Chung Tseng ,  Chi Hsi Wu ,  Wei Ting Chien

发明人： Fan Chung Tseng ,  Chi Hsi Wu ,  Wei Ting Chien

IPC分类号： H01L21/768 ,  G03F1/68 ,  G03F1/00

CPC分类号： H01L21/76807 ,  G03F1/50 ,  G03F1/54 ,  H01L2221/1021

摘要： A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two lithography steps: one to mask and expose the via, and a second step to mask and expose the trench interconnection. The novel method for creating a dual damascene structure allows for a smaller number of processing steps, thus reducing the processing time needed to complete the dual damascene structure. In addition, a lower number of masks may be needed. The exemplary mask or reticle used within the process incorporates different regions possessing different transmission rates. During the exposing step, light from an exposing source passes through the mask to expose a portion of the photoresist layer on top of the wafer. Depending on the transmission rate of the different regions, different thickness of the photoresist layer are exposed and later removed by a developing solution, which allows a subsequent etch process to remove portions of both the dielectric layer and photoresist layer to create a dual damascene structure.

摘要翻译： 一种用于仅使用一个光刻和掩蔽步骤来创建双镶嵌结构的方法。 传统的双镶嵌结构使用两个光刻步骤：一个用于掩蔽和暴露通孔，以及第二步骤，以掩蔽和暴露沟槽互连。 用于创建双镶嵌结构的新颖方法允许较少数量的处理步骤，从而减少完成双镶嵌结构所需的处理时间。 此外，可能需要较少数量的掩模。 在该过程中使用的示例性掩模或掩模版包含具有不同透射率的不同区域。 在曝光步骤期间，来自曝光源的光穿过掩模以暴露晶片顶部上的光致抗蚀剂层的一部分。 取决于不同区域的透射率，曝光不同厚度的光致抗蚀剂层，随后通过显影液去除，这使得随后的蚀刻工艺能够去除介电层和光致抗蚀剂层的部分以产生双镶嵌结构。

公开(公告)号：US07205588B2

公开(公告)日：2007-04-17

申请号：US10856065

申请日：2004-05-28

申请人： Shin-Puu Jeng ,  Chi-Hsi Wu ,  Shang Y. Hou

发明人： Shin-Puu Jeng ,  Chi-Hsi Wu ,  Shang Y. Hou

IPC分类号： H01L27/10

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a metal fuse comprising the following steps. A structure is provided having exposed adjacent metal structures. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having via openings 2 exposing at least a portion of the exposed adjacent metal structures. A metal fuse portion is formed between at least two of the adjacent metal structures without additional photolithography, etch or deposition processes. The metal fuse portion including a portion having a nominal mass and a sub-portion of the portion having a mass less than the nominal mass so that the metal fuse portion is more easily disconnected at the less massive sub-portion during programming of the metal fuse portion.

摘要翻译： 一种形成金属保险丝的方法，包括以下步骤。 提供具有暴露的相邻金属结构的结构。 在该结构上形成图形化的介电层。 具有通孔2的图案化介电层暴露出相邻的金属结构的至少一部分。 金属熔丝部分形成在至少两个相邻的金属结构之间，无需额外的光刻，蚀刻或沉积工艺。 金属熔断器部分包括具有标称质量的部分和该部分的子部分具有小于标称质量的部分，使得金属熔丝部分在金属熔丝编程期间在较小质量的子部分处更容易断开 一部分。

公开(公告)号：US06239007B1

公开(公告)日：2001-05-29

申请号：US09513268

申请日：2000-02-24

申请人： Chi-Hsi Wu

发明人： Chi-Hsi Wu

IPC分类号： H01L213205

CPC分类号： H01L21/28114

摘要： A method of forming a T-shaped gate. Two insulation layers, each having a different etching rate, are sequentially formed over a conventional gate structure. A planarization of the insulation layer is next carried out. Utilizing the difference in etching rate between the two insulation layers, the insulation layer above the gate structure is removed to expose the gate structure. A conductive layer is then formed over the exposed gate structure. Another planarization is carried out so that only the portion of conductive layer above the gate structure is retained. While using the conductive layer above the gate structure as an etching mask, the two insulation layers are removed. A silicide process is carried out to form a silicide layer over the conductive layer.

摘要翻译： 一种形成T形门的方法。 在常规栅极结构上依次形成两个具有不同蚀刻速率的绝缘层。 接下来进行绝缘层的平坦化。 利用两个绝缘层之间的蚀刻速率的差异，去除栅极结构之上的绝缘层以露出栅极结构。 然后在暴露的栅极结构上形成导电层。 进行另一个平坦化，使得仅保留栅极结构上方的导电层的部分。 当使用栅极结构上方的导电层作为蚀刻掩模时，去除两个绝缘层。 进行硅化处理以在导电层上形成硅化物层。

公开(公告)号：US6017815A

公开(公告)日：2000-01-25

申请号：US947939

申请日：1997-10-09

申请人： Chi-Hsi Wu

发明人： Chi-Hsi Wu

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76834 ,  Y10S438/97

摘要： A method of fabricating a border-less via. A semiconductor substrate which comprises patterned metal lines, a gap therebetween, and a first dielectric layer filled within the gap is provide. A second insulating layer is formed over the metal lines and the first dielectric layer. Using a photomask, the second dielectric layer is patterned and etched to form a via. A conductive plug is formed within the via and a second conductive layer is formed over the fourth conductive layer. Thus, the first and second conductive layers are connected by the conductive plug.

摘要翻译： 一种制造无边界通孔的方法。 提供包括图案化金属线，其间的间隙和填充在间隙内的第一电介质层的半导体衬底。 在金属线和第一介电层上形成第二绝缘层。 使用光掩模，对第二介电层进行图案化和蚀刻以形成通孔。 导电插塞形成在通孔内，第二导电层形成在第四导电层上。 因此，第一和第二导电层通过导电插塞连接。

公开(公告)号：US5946583A

公开(公告)日：1999-08-31

申请号：US972316

申请日：1997-11-18

申请人： Chi-Hsi Wu

发明人： Chi-Hsi Wu

IPC分类号： H01L21/3105 ,  H01L23/544 ,  H01L21/76

CPC分类号： H01L21/31053 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A method for preventing alignment marks from disappearing after chemical mechanical polishing according to the invention is disclosed. This method, suitable for a substrate on which devices and first alignment marks are already formed, comprise: forming a metal layer on the substrate, thereby forming second alignment marks on the metal layer above the first alignment marks; forming a required metal pattern on the metal layer and removing part of the metal layer on the first alignment marks; forming a first dielectric layer, an etching stop and a second dielectric layer over the substrate, thereby forming third alignment marks, fourth alignment marks and fifth alignment marks on the first dielectric layer, etching stop and second dielectric layer, respectively; performing chemical mechanical polishing, causing the disappearance of the fifth alignment marks; and forming contact windows in the first dielectric layer and clear out windows on the fourth alignment marks to make said fourth alignment marks reappear. Furthermore, the method for preventing alignment marks from disappearing after chemical mechanical polishing according to the invention not only makes the required alignment marks reappear, but also simplifies the semiconductor process, that is, unlike the prior art, no extra photolithography and etching is required in the invention, because the contact windows and clear out windows are formed simultaneously.

公开(公告)号：US08729634B2

公开(公告)日：2014-05-20

申请号：US13525050

申请日：2012-06-15

申请人： Chun-Liang Shen ,  Kuo-Ching Tsai ,  Hou-Ju Li ,  Chun-Sheng Liang ,  Kao-Ting Lai ,  Kuo-Chiang Ting ,  Chi-Hsi Wu

发明人： Chun-Liang Shen ,  Kuo-Ching Tsai ,  Hou-Ju Li ,  Chun-Sheng Liang ,  Kao-Ting Lai ,  Kuo-Chiang Ting ,  Chi-Hsi Wu

IPC分类号： H01L21/762 ,  H01L29/06

CPC分类号： H01L29/1054 ,  H01L29/66818 ,  H01L29/7853 ,  H01L29/7854

摘要： An integrated circuit device includes a fin at least partially embedded in a shallow trench isolation (STI) region and extending between a source and a drain. The fin is formed from a first semiconductor material and having a trimmed portion between first and second end portions. A cap layer, which is formed from a second semiconductor material, is disposed over the trimmed portion of the fin to form a high mobility channel. A gate electrode structure is formed over the high mobility channel and between the first and second end portions.

摘要翻译： 集成电路器件包括至少部分地嵌入在浅沟槽隔离（STI）区域中并且在源极和漏极之间延伸的翅片。 翅片由第一半导体材料形成，并且在第一和第二端部之间具有修剪部分。 由第二半导体材料形成的盖层设置在翅片的修剪部分之上以形成高迁移率通道。 栅电极结构形成在高迁移率通道上，并在第一和第二端部之间。