RAISE S/D FOR GATE-LAST ILD0 GAP FILLING
    5.
    发明申请
    RAISE S/D FOR GATE-LAST ILD0 GAP FILLING 审中-公开
    GIS-LAST ILD0 GAP填充的RAISE S / D

    公开(公告)号:US20100078728A1

    公开(公告)日:2010-04-01

    申请号:US12546475

    申请日:2009-08-24

    摘要: The present disclosure provides an integrated circuit having metal gate stacks. The integrated circuit includes a semiconductor substrate; a gate stack disposed on the semiconductor substrate, wherein the gate stack includes a high k dielectric layer and a first metal layer disposed on the high k dielectric layer; and a raised source/drain region configured on a side of the gate stack and formed by an epitaxy process, wherein the semiconductor substrate includes a silicon germanium (SiGe) feature underlying the raised source/drain region.

    摘要翻译: 本公开提供了具有金属栅极堆叠的集成电路。 集成电路包括半导体衬底; 设置在所述半导体衬底上的栅极堆叠,其中所述栅极堆叠包括高k电介质层和设置在所述高k电介质层上的第一金属层; 以及构造在所述栅极堆叠侧并通过外延工艺形成的凸起的源极/漏极区域,其中所述半导体衬底包括位于所述升高的源极/漏极区域下方的硅锗(SiGe)特征。