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公开(公告)号:US20100001369A1
公开(公告)日:2010-01-07
申请号:US12471091
申请日:2009-05-22
申请人: Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu
发明人: Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu
IPC分类号: H01L27/06 , H01L21/8249
CPC分类号: H01L21/8249 , H01L27/0623 , H01L27/0629 , H01L27/0635
摘要: A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.
摘要翻译: 提供一种半导体器件,其包括具有第一区域和第二区域的半导体衬底,在第一区域中形成有金属栅极的晶体管,形成在第二区域中的隔离结构,形成在隔离结构中的至少一个接合器件 第二区域,以及形成在第二区域中的隔离结构上方的停止结构。
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公开(公告)号:US09368628B2
公开(公告)日:2016-06-14
申请号:US13542468
申请日:2012-07-05
申请人: Hou-Ju Li , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
发明人: Hou-Ju Li , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
CPC分类号: H01L29/7848 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/66636 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要: An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.
摘要翻译: 集成电路器件包括鳍状物,栅极电极结构下方具有栅极区域,设置在鳍状物的末端以外的源极/漏极区域以及围绕源极/漏极区域的嵌入部分形成的第一共形层。 第一共形层的垂直侧壁平行于栅极区域定向。
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公开(公告)号:US20140008736A1
公开(公告)日:2014-01-09
申请号:US13542468
申请日:2012-07-05
申请人: Hou-Ju Li , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
发明人: Hou-Ju Li , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
IPC分类号: H01L29/78 , H01L21/336
CPC分类号: H01L29/7848 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/66636 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要: An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.
摘要翻译: 集成电路器件包括鳍状物,栅极电极结构下方具有栅极区域,设置在鳍状物的末端以外的源极/漏极区域以及围绕源极/漏极区域的嵌入部分形成的第一共形层。 第一共形层的垂直侧壁平行于栅极区域定向。
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公开(公告)号:US20130334606A1
公开(公告)日:2013-12-19
申请号:US13525050
申请日:2012-06-15
申请人: Chun-Liang Shen , Kuo-Ching Tsai , Hou-Ju Li , Chun-Sheng Liang , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
发明人: Chun-Liang Shen , Kuo-Ching Tsai , Hou-Ju Li , Chun-Sheng Liang , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
IPC分类号: H01L29/78 , H01L21/336
CPC分类号: H01L29/1054 , H01L29/66818 , H01L29/7853 , H01L29/7854
摘要: An integrated circuit device includes a fin at least partially embedded in a shallow trench isolation (STI) region and extending between a source and a drain. The fin is formed from a first semiconductor material and having a trimmed portion between first and second end portions. A cap layer, which is formed from a second semiconductor material, is disposed over the trimmed portion of the fin to form a high mobility channel. A gate electrode structure is formed over the high mobility channel and between the first and second end portions.
摘要翻译: 集成电路器件包括至少部分地嵌入在浅沟槽隔离(STI)区域中并且在源极和漏极之间延伸的翅片。 翅片由第一半导体材料形成,并且在第一和第二端部之间具有修剪部分。 由第二半导体材料形成的盖层设置在翅片的修剪部分之上以形成高迁移率通道。 栅电极结构形成在高迁移率通道上,并在第一和第二端部之间。
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公开(公告)号:US20100078728A1
公开(公告)日:2010-04-01
申请号:US12546475
申请日:2009-08-24
申请人: Hou-Ju Li , Chung Long Cheng , Kong-Beng Thei , Harry Chuang
发明人: Hou-Ju Li , Chung Long Cheng , Kong-Beng Thei , Harry Chuang
IPC分类号: H01L27/092 , H01L29/78 , H01L21/8238
CPC分类号: H01L21/823425 , H01L21/823814 , H01L29/165 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66628 , H01L29/7848
摘要: The present disclosure provides an integrated circuit having metal gate stacks. The integrated circuit includes a semiconductor substrate; a gate stack disposed on the semiconductor substrate, wherein the gate stack includes a high k dielectric layer and a first metal layer disposed on the high k dielectric layer; and a raised source/drain region configured on a side of the gate stack and formed by an epitaxy process, wherein the semiconductor substrate includes a silicon germanium (SiGe) feature underlying the raised source/drain region.
摘要翻译: 本公开提供了具有金属栅极堆叠的集成电路。 集成电路包括半导体衬底; 设置在所述半导体衬底上的栅极堆叠,其中所述栅极堆叠包括高k电介质层和设置在所述高k电介质层上的第一金属层; 以及构造在所述栅极堆叠侧并通过外延工艺形成的凸起的源极/漏极区域,其中所述半导体衬底包括位于所述升高的源极/漏极区域下方的硅锗(SiGe)特征。
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公开(公告)号:US08729634B2
公开(公告)日:2014-05-20
申请号:US13525050
申请日:2012-06-15
申请人: Chun-Liang Shen , Kuo-Ching Tsai , Hou-Ju Li , Chun-Sheng Liang , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
发明人: Chun-Liang Shen , Kuo-Ching Tsai , Hou-Ju Li , Chun-Sheng Liang , Kao-Ting Lai , Kuo-Chiang Ting , Chi-Hsi Wu
IPC分类号: H01L21/762 , H01L29/06
CPC分类号: H01L29/1054 , H01L29/66818 , H01L29/7853 , H01L29/7854
摘要: An integrated circuit device includes a fin at least partially embedded in a shallow trench isolation (STI) region and extending between a source and a drain. The fin is formed from a first semiconductor material and having a trimmed portion between first and second end portions. A cap layer, which is formed from a second semiconductor material, is disposed over the trimmed portion of the fin to form a high mobility channel. A gate electrode structure is formed over the high mobility channel and between the first and second end portions.
摘要翻译: 集成电路器件包括至少部分地嵌入在浅沟槽隔离(STI)区域中并且在源极和漏极之间延伸的翅片。 翅片由第一半导体材料形成,并且在第一和第二端部之间具有修剪部分。 由第二半导体材料形成的盖层设置在翅片的修剪部分之上以形成高迁移率通道。 栅电极结构形成在高迁移率通道上,并在第一和第二端部之间。
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公开(公告)号:US08125051B2
公开(公告)日:2012-02-28
申请号:US12471091
申请日:2009-05-22
申请人: Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu , Tzung-Chi Lee
发明人: Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu , Tzung-Chi Lee
IPC分类号: H01L27/06 , H01L21/70 , H01L21/338 , H01L21/302
CPC分类号: H01L21/8249 , H01L27/0623 , H01L27/0629 , H01L27/0635
摘要: A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.
摘要翻译: 提供一种半导体器件,其包括具有第一区域和第二区域的半导体衬底,在第一区域中形成有金属栅极的晶体管,形成在第二区域中的隔离结构,形成在隔离结构中的至少一个接合器件 第二区域,以及形成在第二区域中的隔离结构上方的停止结构。
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