公开(公告)号：US20140191333A1

公开(公告)日：2014-07-10

申请号：US13735949

申请日：2013-01-07

申请人： Chun-Wei CHANG ,  Yi-An LIN ,  Neng-Kuo CHEN ,  Sey-Ping SUN ,  Clement Hsingjen WANN ,  Yu-Lien HUANG

发明人： Chun-Wei CHANG ,  Yi-An LIN ,  Neng-Kuo CHEN ,  Sey-Ping SUN ,  Clement Hsingjen WANN ,  Yu-Lien HUANG

IPC分类号： H01L29/06 ,  H01L21/02

CPC分类号： H01L21/022 ,  H01L29/66545

摘要： This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.

摘要翻译： 该描述涉及包括在衬底上形成层间电介质（ILD）层和虚拟栅极结构并在ILD层的顶部形成腔的方法。 该方法还包括形成保护层以填充空腔。 该方法还包括平坦化保护层。 平坦化保护层的顶表面与虚拟栅结构的顶表面平齐。 该描述还涉及包括第一和第二栅极结构以及形成在衬底上的ILD层的半导体器件。 半导体器件还包括形成在ILD层上的保护层，保护层具有与ILD层不同的蚀刻选择性，其中保护层的顶表面与第一和第二栅极结构的顶表面平齐。

公开(公告)号：US20140042491A1

公开(公告)日：2014-02-13

申请号：US13572494

申请日：2012-08-10

申请人： Neng-Kuo CHEN ,  Clement Hsingjen WANN ,  Yi-An LIN ,  Chun-Wei CHANG ,  Sey-Ping SUN

发明人： Neng-Kuo CHEN ,  Clement Hsingjen WANN ,  Yi-An LIN ,  Chun-Wei CHANG ,  Sey-Ping SUN

IPC分类号： H01L29/38 ,  H01L21/306

CPC分类号： H01L29/66545 ,  H01L21/28123 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.

摘要翻译： 该描述涉及场效应晶体管的栅电极。 场效应晶体管的示例性结构包括：衬底; 位于所述基板上方的包括第一顶表面和侧壁的栅电极; 至少部分地设置在所述栅电极的一侧的所述衬底中的源极/漏极（S / D）区域; 在所述侧壁上的间隔物分布在所述栅电极和所述S / D区之间; 以及与所述间隔物相邻的接触蚀刻停止层（CESL），并且还包括在所述S / D区域上延伸的部分，其中所述部分具有与所述第一顶表面基本上共面的第二顶表面。

公开(公告)号：US20080251851A1

公开(公告)日：2008-10-16

申请号：US11734673

申请日：2007-04-12

申请人： James N. PAN ,  Sey-Ping SUN ,  Andrew M. WAITE

发明人： James N. PAN ,  Sey-Ping SUN ,  Andrew M. WAITE

IPC分类号： H01L21/8238 ,  H01L29/94

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  H01L2924/0002 ,  Y10S438/938 ,  H01L2924/00

摘要： A strain enhanced semiconductor device and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material in the source and drain regions of the device to induce a strain in the device channel. Thin metal silicide contacts are formed to the source and drain regions so as not to relieve the induced strain. A layer of conductive material is selectively deposited in contact with the thin metal silicide contacts, and metallized contacts are formed to the conductive material.

摘要翻译： 提供一种应变增强型半导体器件及其制造方法。 一种方法包括将应变诱导半导体材料嵌入在器件的源极和漏极区域中以在器件沟道中引起应变。 在源极和漏极区域形成薄金属硅化物触点，以免减轻诱发的应变。 选择性地沉积与薄金属硅化物触点接触的导电材料层，并且将金属化触点形成为导电材料。