公开(公告)号：US08041912B2

公开(公告)日：2011-10-18

申请号：US11863254

申请日：2007-09-28

申请人： Yu-Lan Kuo ,  Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Yu-Lan Kuo ,  Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G06F12/00

CPC分类号： G11C8/20 ,  G06F21/79 ,  G11C16/22

摘要： A memory device comprises a memory array, a status register coupled with the memory array, and a security register coupled with the memory array and the status register. The memory array contains a number of memory blocks configured to have independent access control. The status register includes at least one protection bit indicative of a write-protection status of at least one corresponding block of the memory blocks that corresponds to the protection bit. The security register includes at least one register-protection bit. The register-protection bit is programmable to a memory-protection state for preventing a state change of at least the protection bit of the status register. The register-protection bit is configured to remain in the memory-protection state until the resetting of the memory device.

摘要翻译： 存储器件包括存储器阵列，与存储器阵列耦合的状态寄存器，以及与存储器阵列和状态寄存器耦合的安全寄存器。 存储器阵列包含被配置为具有独立访问控制的多个存储器块。 状态寄存器包括至少一个保护位，指示对应于保护位的存储器块的至少一个相应块的写保护状态。 安全寄存器包括至少一个寄存器保护位。 寄存器保护位可编程为存储器保护状态，以防止至少状态寄存器的保护位的状态改变。 寄存器保护位被配置为保持存储器保护状态，直到存储器件的复位。

公开(公告)号：US20080005434A1

公开(公告)日：2008-01-03

申请号：US11748984

申请日：2007-05-15

申请人： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Yu-Lan Kuo

发明人： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Yu-Lan Kuo

IPC分类号： G06F13/00

CPC分类号： G06F13/4291

摘要： Various embodiments increase the speed of communication over a multi-mode bus by communicating data over multiple pins in the same direction. The bus includes multiple data communication pins communicating over the bus. The bus includes a chip select pin indicating whether communication is occurring between the integrated circuit and another integrated circuit. The bus includes a clock pin. The bus includes a mode control circuit. In one mode, two of the data communication pins communicate in opposite directions between the integrated circuit and another integrated circuit. In another mode, two of the data communication pins communicate in a same direction between the integrated circuit and another integrated circuit. In some embodiments, the bus follows a Serial Peripheral Interface standard. In various embodiments, data is communicated from the integrated circuit to another integrated circuit, or from another integrated circuit to the integrated circuit.

摘要翻译： 各种实施例通过在相同方向上在多个引脚上传送数据来增加多模总线上的通信速度。 总线包括通过总线通信的多个数据通信引脚。 总线包括芯片选择引脚，指示集成电路和另一集成电路之间是否发生通信。 总线包括一个时钟引脚。 总线包括模式控制电路。 在一种模式中，两个数据通信引脚在集成电路和另一个集成电路之间的相反方向上通信。 在另一种模式中，两个数据通信引脚在集成电路和另一个集成电路之间沿相同的方向通信。 在一些实施例中，总线遵循串行外设接口标准。 在各种实施例中，数据从集成电路传送到另一集成电路，或从另一集成电路传送到集成电路。

公开(公告)号：US20110238939A1

公开(公告)日：2011-09-29

申请号：US13155404

申请日：2011-06-08

申请人： Yu-Lan Kuo ,  Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Yu-Lan Kuo ,  Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G06F12/14

CPC分类号： G11C8/20 ,  G06F21/79 ,  G11C16/22

摘要： A memory device comprises a memory array, a status register, a status-register write-protect bit and a security register. The memory array contains a number of memory blocks. The status register includes at least one protection bit indicative of a protection status of at least one corresponding block of the memory blocks. The status-register write-protect bit is coupled with the status register for preventing a state change of the at least one protection bit. The security register includes at least one register-protection bit for preventing the state change in one of the at least one protection bit of the status register and the status-register write-protect bit.

摘要翻译： 存储器件包括存储器阵列，状态寄存器，状态寄存器写保护位和安全寄存器。 存储器阵列包含许多存储器块。 状态寄存器包括至少一个指示存储块的至少一个相应块的保护状态的保护位。 状态寄存器写保护位与状态寄存器耦合以防止至少一个保护位的状态改变。 安全寄存器包括至少一个用于防止状态寄存器的至少一个保护位和状态寄存器写保护位之一的状态改变的寄存器保护位。

公开(公告)号：US08190840B2

公开(公告)日：2012-05-29

申请号：US13155404

申请日：2011-06-08

申请人： Yu-Lan Kuo ,  Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Yu-Lan Kuo ,  Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G11C8/20 ,  G06F21/79 ,  G11C16/22

摘要： A memory device comprises a memory array, a status register, a status-register write-protect bit and a security register. The memory array contains a number of memory blocks. The status register includes at least one protection bit indicative of a protection status of at least one corresponding block of the memory blocks. The status-register write-protect bit is coupled with the status register for preventing a state change of the at least one protection bit. The security register includes at least one register-protection bit for preventing the state change in one of the at least one protection bit of the status register and the status-register write-protect bit.

摘要翻译： 存储器件包括存储器阵列，状态寄存器，状态寄存器写保护位和安全寄存器。 存储器阵列包含许多存储器块。 状态寄存器包括至少一个指示存储块的至少一个相应块的保护状态的保护位。 状态寄存器写保护位与状态寄存器耦合以防止至少一个保护位的状态改变。 安全寄存器包括至少一个用于防止状态寄存器的至少一个保护位和状态寄存器写保护位之一的状态改变的寄存器保护位。

公开(公告)号：US08203896B2

公开(公告)日：2012-06-19

申请号：US12911173

申请日：2010-10-25

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

IPC分类号： G11C7/00 ,  G11C11/50 ,  G11C7/04

CPC分类号： G11C29/022 ,  G11C29/02

摘要： A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.

摘要翻译： 提供了一种存储芯片及其操作方法。 存储器芯片包括多个焊盘。 该方法包括分别将多个第一测试信号输入到焊盘，其中对应于两个物理相邻的焊盘的第一测试信号是互补的; 将多个分别连续到第一测试信号的第二测试信号输入到焊盘，其中对应于每个焊盘的第一测试信号和第二测试信号是互补的; 以及如果所述第一测试信号和所述第二测试信号被所述存储芯片成功接收，则从所述存储器芯片输出预期数据。

公开(公告)号：US08891312B2

公开(公告)日：2014-11-18

申请号：US13453312

申请日：2012-04-23

申请人： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C16/14 ,  G11C16/16 ,  G11C16/344

摘要： Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.

摘要翻译： 非易失性存储器阵列的存储单元的特征在于包括至少一个擦除的阈值电压范围和编程的阈值电压范围的多个阈值电压范围之一。 响应于擦除非易失性存储器阵列的一组存储单元的擦除命令，执行至少包括预编程相位和擦除阶段的多个相位。 预编程相位对组内的阈值电压中的第一组存储器单元进行编程，并且不对组中擦除的阈值电压范围内的阈值电压的组中的第二组存储器单元进行编程 。 通过不对第二组存储器单元进行编程，如果第二组存储器单元与第一组存储器单元一起被编程，那么执行预编程相位更快。

公开(公告)号：US20110038218A1

公开(公告)日：2011-02-17

申请号：US12911173

申请日：2010-10-25

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

IPC分类号： G11C29/08

CPC分类号： G11C29/022 ,  G11C29/02

摘要： A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.

摘要翻译： 提供了一种存储芯片及其操作方法。 存储器芯片包括多个焊盘。 该方法包括分别将多个第一测试信号输入到焊盘，其中对应于两个物理相邻的焊盘的第一测试信号是互补的; 将多个分别连续到第一测试信号的第二测试信号输入到焊盘，其中对应于每个焊盘的第一测试信号和第二测试信号是互补的; 以及如果所述第一测试信号和所述第二测试信号被所述存储芯片成功接收，则从所述存储器芯片输出预期数据。

公开(公告)号：US20090116293A1

公开(公告)日：2009-05-07

申请号：US11976975

申请日：2007-10-30

申请人： Chun-Yi Lee ,  Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chun-Yi Lee ,  Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/06 ,  G11C8/08 ,  G11C5/02

CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C16/08

摘要： A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line comprises a start terminal connected to an output terminal of the first word line driver. The first switch is connected to a second operational voltage and an end terminal of the first word line. The second operational voltage is not smaller than the first operational voltage. When the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage.

摘要翻译： 公开了一种用于对其字线进行充电的存储器和方法。 存储器包括第一字线驱动器，第一字线和第一开关。 第一字线驱动器连接到用于接收第一控制信号的第一操作电压。 第一字线包括连接到第一字线驱动器的输出端的起始端。 第一开关连接到第一字线的第二工作电压和端子。 第二工作电压不小于第一工作电压。 当第一字线驱动器由第一控制信号控制以开始向第一字线充电时，第一开关同时导通，以为第一字线提供另一充电路径，直到第一字线被充电到第一操作 电压。

公开(公告)号：US20130279265A1

公开(公告)日：2013-10-24

申请号：US13453312

申请日：2012-04-23

申请人： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C16/14 ,  G11C16/16 ,  G11C16/344

摘要： Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.

摘要翻译： 非易失性存储器阵列的存储单元的特征在于包括至少一个擦除的阈值电压范围和编程的阈值电压范围的多个阈值电压范围之一。 响应于擦除非易失性存储器阵列的一组存储单元的擦除命令，执行至少包括预编程相位和擦除阶段的多个相位。 预编程相位对组内的阈值电压中的第一组存储器单元进行编程，并且不对组中擦除的阈值电压范围内的阈值电压的组中的第二组存储器单元进行编程 。 通过不对第二组存储器单元进行编程，如果第二组存储器单元与第一组存储器单元一起被编程，那么执行预编程相位更快。

公开(公告)号：US08411509B2

公开(公告)日：2013-04-02

申请号：US11976975

申请日：2007-10-30

申请人： Chun-Yi Lee ,  Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chun-Yi Lee ,  Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C16/08

摘要： A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line comprises a start terminal connected to an output terminal of the first word line driver. The first switch is connected to a second operational voltage and an end terminal of the first word line. The second operational voltage is not smaller than the first operational voltage. When the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage.