公开(公告)号：US08427347B1

公开(公告)日：2013-04-23

申请号：US13075656

申请日：2011-03-30

申请人： Chung Shien Chai ,  Yin Chong Hew

发明人： Chung Shien Chai ,  Yin Chong Hew

IPC分类号： H03M7/38

CPC分类号： H03M7/30

摘要： A method of compressing data is provided. In one implementation, the method includes compressing data with a plurality of compression schemes, where the compressing is computer implemented. Also, in one implementation, the plurality of compression schemes include a first compression scheme and a second compression scheme and the compressing includes compressing a first portion of the data with the first compression scheme and compressing a second portion of the data with the second compression scheme, where the second compression scheme is different from the first compression scheme. In one implementation, the method further includes determining a suitable compression scheme from the plurality of compression schemes with which to compress each portion of the data, where the determining is computer implemented. In one implementation, the data is configuration data for configuring an IC.

摘要翻译： 提供了压缩数据的方法。 在一个实现中，该方法包括使用多个压缩方案压缩数据，其中压缩是计算机实现的。 此外，在一个实施方式中，多个压缩方案包括第一压缩方案和第二压缩方案，并且压缩包括用第一压缩方案压缩数据的第一部分，并用第二压缩方案压缩数据的第二部分 ，其中第二压缩方案与第一压缩方案不同。 在一个实现中，该方法还包括从用于压缩数据的每个部分的多个压缩方案中确定合适的压缩方案，其中确定是计算机实现的。 在一个实现中，数据是用于配置IC的配置数据。

公开(公告)号：US20220405453A1

公开(公告)日：2022-12-22

申请号：US17854341

申请日：2022-06-30

申请人： Rahul Pal ,  Ashish Gupta ,  Navid Azizi ,  Jeffrey Schulz ,  Yin Chong Hew ,  Thuyet Ngo ,  George Chong Hean Ooi ,  Vikrant Kapila ,  Kok Kee Looi

发明人： Rahul Pal ,  Ashish Gupta ,  Navid Azizi ,  Jeffrey Schulz ,  Yin Chong Hew ,  Thuyet Ngo ,  George Chong Hean Ooi ,  Vikrant Kapila ,  Kok Kee Looi

IPC分类号： G06F30/34 ,  G06F9/54 ,  G06F9/30

摘要： Systems or methods of the present disclosure may provide a programmable logic device including a network-on-chip (NoC) to facilitate data transfer between one or more main intellectual property components (main IP) and one or more secondary intellectual property components (secondary IP). To reduce or prevent excessive congestion on the NoC, the NoC may include one or more traffic throttlers that may receive feedback from a data buffer, a main bridge, or both and adjust data injection rate based on the feedback. Additionally, the NoC may include a data mapper to enable data transfer to be remapped from a first destination to a second destination if congestion is detected at the first destination.

公开(公告)号：US08819391B1

公开(公告)日：2014-08-26

申请号：US13289916

申请日：2011-11-04

申请人： Lai Khuan Lock ,  Yin Chong Hew

发明人： Lai Khuan Lock ,  Yin Chong Hew

IPC分类号： G06F12/10 ,  G11C29/18

CPC分类号： G06F12/1027 ,  G11C29/44 ,  G11C29/76 ,  G11C2029/1806 ,  G11C2029/4402

摘要： Methods and apparatuses for managing unusable blocks in a memory module are provided. The memory table may include a plurality of unusable block addresses in the memory module where the plurality of unusable block addresses is arranged in a sequential order in the memory table. A number of unusable blocks in the memory module is identified by reading a word that represents the number of unusable blocks from the memory table. A first pair of addresses comprises a first unusable block address and a first corresponding mapped memory address. The pair of addresses are read from the memory table and stored in a storage element of a controller. Only a single pair of addresses is stored in the storage element of the controller at any one time according to one embodiment.

摘要翻译： 提供了用于管理存储器模块中的不可用块的方法和装置。 存储器表可以包括存储器模块中的多个不可用的块地址，其中多个不可​​用的块地址按顺序排列在存储器表中。 通过从存储器表中读取表示不可用块的数量的字来识别存储器模块中的多个不可用的块。 第一对地址包括第一不可用块地址和第一对应映射存储器地址。 一对地址从存储器表读取并存储在控制器的存储元件中。 根据一个实施例，只有一对地址在任何一个时间存储在控制器的存储元件中。

公开(公告)号：US08862798B1

公开(公告)日：2014-10-14

申请号：US13310420

申请日：2011-12-02

申请人： Yin Chong Hew

发明人： Yin Chong Hew

IPC分类号： G06F13/12 ,  G06F13/38

CPC分类号： G11C16/26 ,  G06F13/4018 ,  G11C7/1006 ,  G11C2207/107

摘要： An integrated circuit (IC) that enables a fast parallel-to-serial memory data transfer is described. The IC includes a first input output (IO) interface operable to receive a plurality of data in parallel from a memory device, wherein the plurality of data is a binary sequence. The IC also includes a controller receiving the plurality of data from the first IO interface, wherein the controller is operable to generate a compressed data by compressing the plurality of data, wherein a portion of the compressed data provides information on a significant portion of the plurality of data. And the IC also includes a second IO interface receives the compressed data from the controller and serially shifts the compressed data out of the IC.

摘要翻译： 描述了能够进行快速并行到串行存储器数据传输的集成电路（IC）。 IC包括可操作以从存储器装置并行地接收多个数据的第一输入输出（IO）接口，其中所述多个数据是二进制序列。 IC还包括从第一IO接口接收多个数据的控制器，其中控制器可操作以通过压缩多个数据来生成压缩数据，其中压缩数据的一部分提供关于多个数据的重要部分的信息 数据的。 并且IC还包括第二IO接口从控制器接收压缩数据并将压缩数据串行地移出IC。