公开(公告)号：US07359248B2

公开(公告)日：2008-04-15

申请号：US11481022

申请日：2006-07-06

申请人： Chung Zen Chen ,  Jo Yu Wang ,  Fu An Wu

发明人： Chung Zen Chen ,  Jo Yu Wang ,  Fu An Wu

IPC分类号： G11C11/34

CPC分类号： G11C16/24 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642

摘要： Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells. The read method comprises the steps of: (d) reading the MSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by a first verify signal and a second verify signal, and (e) reading the LSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by the first verify signal and a third verify signal. A page buffer is also disclosed to perform the methods for programming and reading a multi-level-cell NAND flash memory device.

摘要翻译： 公开了用于编程和读取具有多个存储器单元的多电平单元NAND闪速存储器件的方法，以减少编程时间和读取时间。 程序方法包括以下步骤：（a）将零状态存储单元，第一状态存储单元，第二状态存储单元和第三状态存储单元编程为零状态，（b）将第二状态存储单元从 通过切换第二状态存储单元的MSB来将零状态转换到第二状态，以及（c）通过切换第一状态存储单元的LSB并将第一状态存储单元的零状态编程为零，将第一状态存储单元从零状态编程为第一状态 通过切换第三状态存储单元的LSB，从第二状态到第三状态的第三状态存储单元。 读取方法包括以下步骤：（d）通过第一验证信号和第二验证信号读取零状态存储器单元，第一状态存储器单元，第二状态存储器单元和第三状态存储器单元的MSB， 以及（e）通过第一验证信号和第三验证信号读取零状态存储器单元，第一状态存储器单元，第二状态存储器单元和第三状态存储器单元的LSB。 还公开了一种页缓冲器来执行用于编程和读取多电平单元NAND闪存器件的方法。

公开(公告)号：US20080008008A1

公开(公告)日：2008-01-10

申请号：US11481022

申请日：2006-07-06

申请人： Chung Zen Chen ,  Jo Yu Wang ,  Fu An Wu

发明人： Chung Zen Chen ,  Jo Yu Wang ,  Fu An Wu

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/24 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642

摘要： Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells. The read method comprises the steps of: (d) reading the MSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by a first verify signal and a second verify signal, and (e) reading the LSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by the first verify signal and a third verify signal. A page buffer is also disclosed to perform the methods for programming and reading a multi-level-cell NAND flash memory device.

摘要翻译： 公开了用于编程和读取具有多个存储器单元的多电平单元NAND闪速存储器件的方法，以减少编程时间和读取时间。 程序方法包括以下步骤：（a）将零状态存储单元，第一状态存储单元，第二状态存储单元和第三状态存储单元编程为零状态，（b）将第二状态存储单元从 通过切换第二状态存储单元的MSB来将零状态转换到第二状态，以及（c）通过切换第一状态存储单元的LSB并将第一状态存储单元的零状态编程为零，将第一状态存储单元从零状态编程为第一状态 通过切换第三状态存储单元的LSB，从第二状态到第三状态的第三状态存储单元。 读取方法包括以下步骤：（d）通过第一验证信号和第二验证信号读取零状态存储器单元，第一状态存储器单元，第二状态存储器单元和第三状态存储器单元的MSB， 以及（e）通过第一验证信号和第三验证信号读取零状态存储器单元，第一状态存储器单元，第二状态存储器单元和第三状态存储器单元的LSB。 还公开了一种页缓冲器来执行用于编程和读取多电平单元NAND闪存器件的方法。

公开(公告)号：US07336543B2

公开(公告)日：2008-02-26

申请号：US11358767

申请日：2006-02-21

申请人： Chung Zen Chen ,  Jo Yu Wang

发明人： Chung Zen Chen ,  Jo Yu Wang

IPC分类号： G11C7/10 ,  G11C16/04

CPC分类号： G11C8/10 ,  G11C7/1042 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/102 ,  G11C16/105 ,  G11C16/26 ,  G11C2216/14

摘要： A non-volatile memory device with a page buffer having dual registers includes a memory cell array, a selector circuit and a page buffer circuit, the selector circuit being coupled to an exterior data line, the page buffer circuit including a first register and a second register being coupled between the memory cell array and the selector circuit, and the first register and second register being commonly coupled through a sense node. The first and second registers alternately write data to the memory cell array for programming. As one of the first and second registers performs programming, the other register stores data from the data line concurrently. In other words, the second register stores data from the data line when the first register is in programming, whereas the first register stores data from the data line when the second register is in programming.

摘要翻译： 具有双寄存器的页缓冲器的非易失性存储器件包括存储单元阵列，选择器电路和页缓冲电路，选择器电路耦合到外部数据线，该页缓冲电路包括第一寄存器和第二寄存器 寄存器耦合在存储单元阵列和选择器电路之间，并且第一寄存器和第二寄存器通常通过感测节点耦合。 第一和第二寄存器交替地将数据写入存储单元阵列用于编程。 作为第一和第二寄存器之一执行编程，其他寄存器同时存储来自数据线的数据。 换句话说，当第一寄存器处于编程时，第二寄存器存储来自数据线的数据，而当第二寄存器处于编程时，第一寄存器存储来自数据线的数据。