公开(公告)号：US06737352B2

公开(公告)日：2004-05-18

申请号：US10194630

申请日：2002-07-12

Applicant: Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Ya

Inventor： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Ya

IPC: H01L214763

CPC classification number: H01L21/76802

Abstract: A method to prevent particle generation from sputtering clean is disclosed, the method comprises of forming a dielectric layer on a substrate, forming a nitrogen-containing dielectric layer on the dielectric layer, forming a plurality of contact holes in the dielectric layer and the nitrogen-containing dielectric layer, coating a sacrificial layer into the contact holes and on the nitrogen-containing dielectric layer, removing the sacrificial layer and the nitrogen-containing dielectric layer on top of the dielectric layer, removing said sacrificial layer in said contact holes and performing an argon sputtering clean.

Abstract translation: 公开了一种防止溅射清洁产生颗粒的方法，该方法包括在基板上形成电介质层，在电介质层上形成含氮介电层，在电介质层中形成多个接触孔， 在所述接触孔和所述含氮电介质层上涂覆牺牲层，在所述电介质层的顶部上去除所述牺牲层和所述含氮介电层，去除所述接触孔中的所述牺牲层，并执行 氩气溅射清洗。

公开(公告)号：US06242338B1

公开(公告)日：2001-06-05

申请号：US09422175

申请日：1999-10-22

Applicant: Chung-Shi Liu ,  Shau-Lin Shue ,  Yao-yi Cheng ,  Chen-Hua Yu ,  Mei-Yun Wang

Inventor： Chung-Shi Liu ,  Shau-Lin Shue ,  Yao-yi Cheng ,  Chen-Hua Yu ,  Mei-Yun Wang

IPC: H01L214763

CPC classification number: H01L21/02131 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31629 ,  H01L21/321 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76888

Abstract: A process of forming a thin, protective insulator layer, on the sides of metal interconnect structures, prior to the deposition of a halogen containing, low k dielectric layer, has been developed. The process features the growth of a thin metal nitride, or thin metal oxide layer, on the exposed sides of the metal interconnect structures, via a plasma treatment, performed in either a nitrogen containing, or in a water containing, ambient. The thin layer protects the metal interconnect structure from the corrosive, as well as delamination effects, created by the halogen, or halogen products, contained in overlying low k dielectric layers, such as fluorinated silica glass.

Abstract translation: 已经开发了在沉积含卤素的低k电介质层之前在金属互连结构的侧面上形成薄的保护性绝缘体层的工艺。 该方法的特征在于金属互连结构的暴露侧上通过等离子体处理在含氮或含水环境中进行的金属氮化物或薄金属氧化物层的生长。 薄层保护金属互连结构免受由覆盖在低k电介质层（例如氟化石英玻璃）中的卤素或卤素产物产生的腐蚀性以及分层影响。

公开(公告)号：US07091600B2

公开(公告)日：2006-08-15

申请号：US10791014

申请日：2004-03-02

Applicant: Chung-Shi Liu ,  Shau-Lin Shue

Inventor： Chung-Shi Liu ,  Shau-Lin Shue

IPC: H01L23/48

CPC classification number: H01L21/76829 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76877

Abstract: A common problem associated with damascene structures made of copper inlaid in FSG (fluorinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silicate glass) over the surface of the FSG layer prior to patterning and etching the latter to form the via hole and (for a dual damascene structure) the trench. After over-filling with copper, the structure is planarized using CMP. The USG layer acts both to prevent any fluorine from the FSG layer from reaching the copper and as an end-point detector during CMP. In this way defects that result from copper-fluorine interaction do not form and precise planarization is achieved.

Abstract translation: 与镶嵌在FSG（氟化硅酸盐玻璃）中的铜构成的镶嵌结构相关的常见问题是在结构顶表面附近形成缺陷。 本发明通过在图案化之前放置一层USG（未掺杂的硅酸盐玻璃）以避免这种问题，然后在图案化之前对其进行蚀刻，以形成通孔和（用于双镶嵌结构）沟槽。 用铜填充后，使用CMP对结构进行平面化处理。 USG层既可以防止FSG层中的任何氟达到铜，也可以作为CMP中的终点检测器。 以这种方式，铜 - 氟相互作用产生的缺陷不能形成并且实现精确的平坦化。

公开(公告)号：US06297158B1

公开(公告)日：2001-10-02

申请号：US09583402

申请日：2000-05-31

Applicant: Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L214763

CPC classification number: H01L21/76873 ,  H01L21/76843 ,  H01L21/76864

Abstract: In the presently disclosed invention, a method is provided to avoid damage to a copper interconnect while subjecting the interconnect to chemical-mechanical polishing (CMP). First, a copper barrier layer is formed in a damascene structure. Then, prior to the deposition of copper metal into the damascene openings, a barrier layer is formed on the inside walls of the damascene structure. In a first embodiment, the copper barrier layer is deposited at high temperature. Then, it is cooled down in a prescribed manner. Subsequently, a copper seed layer is formed over the barrier, which is followed by the electro-chemical deposition (ECD) of copper, to form the copper damascene interconnect. Alternatively, in a second embodiment, the copper layer is formed at low temperature. Then it is annealed at a high temperature, followed by wafer cooling. Subsequently, copper seed layer is formed over the barrier layer. Next, ECD copper is formed in the damascene structure. Finally, the interconnect so formed by either of the embodiments is subjected to CMP. It is found that, through the disclosed method of treatment of the barrier layer, process stresses that are normally formed within the barrier layer are relieved, and hence no damage is incurred during the final steps of chemical-mechanical polishing.

Abstract translation: 在本公开的发明中，提供了一种方法，以避免对互连线进行化学机械抛光（CMP）的铜互连的损坏。 首先，在大马士革结构中形成铜阻挡层。 然后，在将铜金属沉积到镶嵌开口之前，在镶嵌结构的内壁上形成阻挡层。 在第一实施例中，铜阻挡层在高温下沉积。 然后，以规定的方式冷却。 随后，在屏障上形成铜籽晶层，随后是铜的电化学沉积（ECD），以形成铜镶嵌互连。 或者，在第二实施例中，铜层在低温下形成。 然后在高温下进行退火，然后进行晶片冷却。 随后，在阻挡层上形成铜籽晶层。 接下来，在镶嵌结构中形成ECD铜。 最后，将由这两个实施例形成的互连件进行CMP处理。 发现通过公开的阻挡层处理方法，通常在阻挡层内形成的工艺应力被释放，因此在化学机械抛光的最终步骤期间不会产生损伤。

公开(公告)号：US06221758B1

公开(公告)日：2001-04-24

申请号：US09225064

申请日：1999-01-04

Applicant: Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L214763

CPC classification number: H01L21/76856 ,  H01L21/76805 ,  H01L21/76843

Abstract: In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole on the bottom in the dielectric layer with the overall trench reaching down to the substrate. Preclean the trench. Form a tantalum film over the dielectric layer including the trench walls, covering the exposed the substrate surface. Fill grain boundaries of the tantalum film with at least one of tantalum oxide and tantalum nitride forming a filled tantalum film. Form a redeposited tantalum layer above the filled tantalum film. Form a copper seed film above the redeposited tantalum film. Plate the device filling the trench with a plated bulk copper layer on the seed film. Planarize the device to expose the top surface of the dielectric layer, removing surplus portions of the filled tantalum film, the copper seed film, and the bulk copper layer. The filled tantalum film is formed by exposing the tantalum to air under STP atmospheric conditions or by exposure to a nitrous oxide (N2O) gas in a plasma at a temperature of about 400° C.

公开(公告)号：US06207568B1

公开(公告)日：2001-03-27

申请号：US09200554

申请日：1998-11-27

Applicant: Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L2144

CPC classification number: H01L21/76841 ,  H01L21/2855 ,  H01L21/28568 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an aluminum containing conductor layer. There is first provided a substrate. There is then formed over the substrate a titanium layer employing an ionized metal plasma bias sputtering method. Finally there is then formed upon the titanium layer an aluminum containing conductor layer. By employing the ionized metal plasma bias sputtering method for forming the titanium layer, the aluminum containing conductor layer is formed with an enhanced (111) crystallographic orientation. The method is particularly useful for forming aluminum containing conductor layers with enhanced electromigration resistance, even under circumstances where there is formed interposed between a titanium layer and an aluminum containing conductor layer a titanium nitride layer.

Abstract translation: 一种形成含铝导体层的方法。 首先提供基板。 然后在衬底上形成采用电离金属等离子体偏置溅射方法的钛层。 最后，在钛层上形成含有铝的导体层。 通过采用用于形成钛层的电离金属等离子体偏压溅射法，形成具有增强（111）晶体取向的含铝导体层。 该方法对于形成具有增强的电迁移电阻的含铝导体层特别有用，即使在钛层和含铝导体层之间形成氮化钛层的情况下也是如此。

公开(公告)号：US20060292860A1

公开(公告)日：2006-12-28

申请号：US11463515

申请日：2006-08-09

Applicant: Chung-Shi Liu ,  Shau-Lin Shue

Inventor： Chung-Shi Liu ,  Shau-Lin Shue

IPC: H01L21/4763

CPC classification number: H01L21/76829 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76877

Abstract: A common problem associated with damascene structures made of copper inlaid in FSG (fluorinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silicate glass) over the surface of the FSG layer prior to patterning and etching the latter to form the via hole and (for a dual damascene structure) the trench. After over-filling with copper, the structure is planarized using CMP. The USG layer acts both to prevent any fluorine from the FSG layer from reaching the copper and as an end-point detector during CMP. In this way defects that result from copper-fluorine interaction do not form and precise planarization is achieved.

Abstract translation: 与镶嵌在FSG（氟化硅酸盐玻璃）中的铜构成的镶嵌结构相关的常见问题是在结构顶表面附近形成缺陷。 本发明通过在图案化之前放置一层USG（未掺杂的硅酸盐玻璃）以避免这种问题，然后在图案化之前对其进行蚀刻，以形成通孔和（用于双镶嵌结构）沟槽。 用铜填充后，使用CMP对结构进行平面化处理。 USG层既可以防止FSG层中的任何氟达到铜，也可以作为CMP中的终点检测器。 以这种方式，铜 - 氟相互作用产生的缺陷不能形成并且实现精确的平坦化。

公开(公告)号：US06723639B1

公开(公告)日：2004-04-20

申请号：US09863223

申请日：2001-05-24

Applicant: Chung-Shi Liu ,  Shau-Lin Shue

Inventor： Chung-Shi Liu ,  Shau-Lin Shue

IPC: H01L2144

CPC classification number: H01L21/76829 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76877

Abstract: A common problem associated with damascene structures made of copper inlaid in FSG (flourinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silicate glass) over the surface of the FSG layer prior to patterning and etching the latter to form the via hole and (for a dual damascene structure) the trench. After over-filling with copper, the structure is planarized using CMP. The USG layer acts both to prevent any flourine from the FSG layer from reaching the copper and as an end-point detector during CMP. In this way defects that result from copper-fluorine interaction do not form and precise planarization is achieved.

Abstract translation: 与镶嵌在FSG（含氟硅酸盐玻璃）中的铜制成的镶嵌结构相关的常见问题是在结构顶表面附近形成缺陷。 本发明通过在图案化之前放置一层USG（未掺杂的硅酸盐玻璃）以避免这种问题，然后在图案化之前对其进行蚀刻，以形成通孔和（用于双镶嵌结构）沟槽。 用铜填充后，使用CMP对结构进行平面化处理。 USG层既可以防止FSG层的任何粉末到达铜，也可以作为CMP中的终点检测器。 以这种方式，铜 - 氟相互作用产生的缺陷不能形成并且实现精确的平坦化。

公开(公告)号：US06353260B2

公开(公告)日：2002-03-05

申请号：US09785106

申请日：2001-02-20

Applicant: Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L2348

CPC classification number: H01L21/76856 ,  H01L21/76805 ,  H01L21/76843

Abstract: In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole on the bottom in the dielectric layer with the overall trench reaching down to the substrate. Preclean the trench. Form a tantalum film over the dielectric layer including the trench walls, covering the exposed the substrate surface. Fill grain boundaries of the tantalum film with at least one of tantalum oxide and tantalum nitride forming a filled tantalum film. Form a redeposited tantalum layer above the filled tantalum film. Form a copper seed film above the redeposited tantalum film. Plate the device filling the trench with a plated bulk copper layer on the seed film. Planarize the device to expose the top surface of the dielectric layer, removing surplus portions of the filled tantalum film, the copper seed film, and the bulk copper layer. The filled tantalum film is formed by exposing the tantalum to air under STP atmospheric conditions or by exposure to a nitrous oxide (N2O) gas in a plasma at a temperature of about 400° C.

Abstract translation: 在通过以下步骤形成其中导电基板被电介质层覆盖的半导体器件中，在电介质层的顶部形成有沟槽线的沟槽和底部的接触孔，其中整个沟槽到达 基质。 清洁沟槽。 在包括沟槽壁的电介质层上形成钽膜，覆盖暴露的衬底表面。 用钽氧化物和氮化钽中的至少一种填充钽膜的晶界，形成填充的钽膜。 在填充的钽膜上方形成再沉积的钽层。 在再沉积的钽膜上方形成铜籽晶膜。 将装有填充沟槽的装置用种子膜上的电镀体铜层铺平。 平面化器件以暴露电介质层的顶表面，去除填充的钽膜，铜籽晶膜和块状铜层的剩余部分。 填充的钽膜通过在STP大气条件下暴露于空气或通过在约400℃的温度下暴露于等离子体中的一氧化二氮（N 2 O）气体而形成。

公开(公告)号：US06277745B1

公开(公告)日：2001-08-21

申请号：US09221965

申请日：1998-12-28

Applicant: Chung-Shi Liu ,  Shau-Lin Shue ,  Syun-Ming Jang ,  Chen-Hua Yu

Inventor： Chung-Shi Liu ,  Shau-Lin Shue ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC: H01L2144

CPC classification number: H01L21/02071 ,  H01L21/321 ,  H01L21/32136 ,  H01L21/76841 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885

Abstract: The present invention relates to a new structure and method for the passivation of copper electrical interconnects for the semiconductor industry. More particularly, the invention details a convenient method for completing the passivation of copper lines after they have been patterned by a dry etch process. The method includes the formation of a sandwich structure consisting of a bottom barrier layer, a copper layer and a top barrier layer. After the sandwich structure is patterned with a dry etch, for example, the resultant exposed copper sidewalls are then passivated by means of a barrier metal spacer process. The fully encapsulated copper lines are highly resistant to oxidation, which is an, otherwise, inherent problem associated with the lack of self passivation/exhibited by bare copper films.

Abstract translation: 本发明涉及用于半导体工业的铜电互连钝化的新结构和方法。 更具体地，本发明详细描述了在通过干蚀刻工艺对其进行图案化之后完成铜线钝化的方便方法。 该方法包括形成由底部阻挡层，铜层和顶部阻挡层组成的夹层结构。 在用干蚀刻图案化夹层结构之后，然后通过阻挡金属间隔物工艺钝化所得到的暴露的铜侧壁。 完全封装的铜线具有很高的抗氧化性，这是另一种与裸铜膜缺乏自钝化/显示相关的固有问题。