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    Method for fabricating semiconductor device with silicided gate
    2.
    发明授权
    Method for fabricating semiconductor device with silicided gate 有权
    用硅化物栅极制造半导体器件的方法

    公开(公告)号：US07678694B2

    公开(公告)日：2010-03-16

    申请号：US11787842

    申请日：2007-04-18

    申请人： Mei-Yun Wang ,  Cheng-Chen Calvin Hsueh

    发明人： Mei-Yun Wang ,  Cheng-Chen Calvin Hsueh

    IPC分类号： H01L21/44

    CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66545

    摘要： A method for fabricating a semiconductor device having a silicided gate that is directed to forming the silicided structures while maintaining gate-dielectric integrity. Initially, a gate structure has, preferably, a poly gate electrode separated from a substrate by a gate dielectric and a metal layer is then deposited over at least the poly gate electrode. The fabrication environment is placed at an elevated temperature. The gate structure may be one of two gate structures included in a dual gate device such as a CMOS device, in which case the respective gates may be formed at different heights (thicknesses) to insure that the silicide forms to the proper phase. The source and drain regions are preferably silicided as well, but in a separate process performed while the gate electrodes are protected by, for example a cap of photoresist or a hardmask structure.

    摘要翻译： 一种用于制造半导体器件的方法，该半导体器件具有硅化物栅极，其被引导以形成硅化物结构，同时保持栅极 - 电介质完整性。 最初，栅极结构优选地具有通过栅极电介质从衬底分离的多晶硅栅极，然后在至少多晶硅栅极上沉积金属层。 制造环境放置在高温下。 栅极结构可以是包括在诸如CMOS器件的双栅极器件中的两个栅极结构之一，在这种情况下，各个栅极可以形成在不同的高度（厚度），以确保硅化物形成适当的相位。 源极和漏极区域也优选是硅化的，但是在通过例如光致抗蚀剂或硬掩模结构的盖保护栅电极的同时进行的单独工艺。

    Method for making low-resistance silicide contacts between closely spaced electrically conducting lines for field effect transistors
    7.
    发明授权
    Method for making low-resistance silicide contacts between closely spaced electrically conducting lines for field effect transistors 有权
    用于场效应晶体管的紧密间隔的导电线之间制造低电阻硅化物接触的方法

    公开(公告)号：US06451701B1

    公开(公告)日：2002-09-17

    申请号：US09993068

    申请日：2001-11-14

    申请人： Mei-Yun Wang ,  Shwangming Jeng ,  Shau-Lin Shue

    发明人： Mei-Yun Wang ,  Shwangming Jeng ,  Shau-Lin Shue

    IPC分类号： H01L21425

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/31155

    摘要： A method for making reliable low-resistance contacts between closely spaced FET gate electrodes having high-aspect-ratio spacings. Polysilicon gate electrodes are formed. A conformal insulating layer is deposited and anisotropically etched back to form sidewall spacers on the gate electrodes. During conventional etch-back, the etch rate of the insulating layer between the closely spaced gate electrodes is slower resulting in a residual oxide that prevents the formation of reliable low-resistance contacts. This residual oxide requires an overetch in a hydrofluoric acid solution prior to forming silicide contacts. The wet overetch results in device degradation. A nitrogen or germanium implant is used to amorphize the oxide and to increase the wet etch rate of the residual oxide. Using this amorphization the wet etch that is commonly used as a pre-clean prior to forming silicide contacts can be used to remove the residual silicon oxide without overetching. The implant also results in a smoother interface between the silicide and the silicon substrate, which results in lower sheet resistance.

    摘要翻译： 一种用于在具有高纵横比间隔的紧密间隔的FET栅电极之间进行可靠的低电阻接触的方法。 形成多晶硅栅电极。 沉积保形绝缘层并各向异性地回蚀以在栅电极上形成侧壁间隔物。 在传统的回蚀期间，绝缘层在紧密间隔的栅电极之间的蚀刻速率较慢，导致残留的氧化物阻止形成可靠的低电阻触点。 在形成硅化物接触之前，该残余氧化物需要在氢氟酸溶液中进行过蚀刻。 湿过滤会导致设备退化。 氮或锗植入物用于使氧化物非晶化并增加残余氧化物的湿蚀刻速率。 使用这种非晶化，通常在形成硅化物接触之前通常用作预清洁的湿法蚀刻可以用于除去剩余的氧化硅而不进行过蚀刻。 该植入物还导致硅化物和硅衬底之间更平滑的界面，这导致较低的薄层电阻。

    Key-hole reduction during tungsten plug formation
    8.
    发明授权
    Key-hole reduction during tungsten plug formation 有权
    钨丝塞形成期间的关键孔减少

    公开(公告)号：US6096651A

    公开(公告)日：2000-08-01

    申请号：US228126

    申请日：1999-01-11

    申请人： Mei-Yun Wang ,  Chen-Hua Yu ,  Shau-Lin Shue

    发明人： Mei-Yun Wang ,  Chen-Hua Yu ,  Shau-Lin Shue

    IPC分类号： H01L21/768 ,  H01L21/302

    CPC分类号： H01L21/76865 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76862

    摘要： The problem of key-hole formation during the filling of small diameter via holes has been overcome by means of soft sputtering in argon after the barrier layer is in place. This sputtering step may be used twice--once to widen the mouth of a newly formed via hole, and a second time after the barrier layer is in place, thereby widening the mouth further (as well as removing oxide from the surface of the barrier layer). In an alternate optional embodiment, widening of the via hole mouth may be limited to a single sputtering step after the barrier layer has been laid down. In either case, this is followed by filling of the via hole which occurs without any key-hole formation.

    摘要翻译： 通过在阻挡层就位之后的氩气中的软溅射，克服了在小直径通孔填充期间形成孔洞的问题。 该溅射步骤可以使用两次一次来加宽新形成的通孔的口，并且在阻挡层就位之后的第二次，从而进一步扩大口（以及从阻挡层的表面去除氧化物） ）。 在替代的可选实施例中，通孔口的加宽可以在阻挡层被铺设之后被限制到单个溅射步骤。 在任一种情况下，随后填充通孔而没有任何键孔形成。