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公开(公告)号：US07237208B1
公开(公告)日：2007-06-26
申请号：US10818711
申请日：2004-04-05
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： To perform functional verification of a digital design that includes one or more datapaths, a formal verification system includes a datapath abstraction tool. The datapath abstraction tool detects a datapath in a circuit design and performs an appropriate abstraction of the datapath. The tool may also deduce datapath elements from identified ones as well as link the abstractions of particular datapath elements. The abstraction tool then passes the circuit design with the abstraction to the verification software to simplifying the formal verification process.
摘要翻译： 为了执行包括一个或多个数据路径的数字设计的功能验证，形式验证系统包括数据路径抽取工具。 数据路径抽象工具检测电路设计中的数据路径，并执行数据路径的适当抽象。 该工具还可以从识别的数据路径元素中推导出数据路径元素，并链接特定数据路径元素的抽象。 然后，抽象工具将抽象的电路设计传递给验证软件，以简化形式验证过程。
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公开(公告)号：US07418678B1
公开(公告)日：2008-08-26
申请号：US10909099
申请日：2004-07-29
申请人： Chung-Wah N Ip , Lawrence Loh , Vigyan Singhal , Howard Wong-Toi
发明人： Chung-Wah N Ip , Lawrence Loh , Vigyan Singhal , Howard Wong-Toi
CPC分类号： G06F17/504 , G06F17/5022
摘要： A counter abstraction tool generates an abstraction model for one or more counters in a circuit design for use with a formal verification system. The tool detects the presence of a counter in a circuit design, identifies one or more special values for the counter, and creates an abstraction for the counter. The tool can automatically perform the abstraction, guide a user in configuring the appropriate abstraction for the counter, or perform a combination of automatic and manual abstraction. The tool may further accommodate related counters.
摘要翻译： 计数器抽象工具为电路设计中的一个或多个计数器生成抽象模型，以便与形式验证系统一起使用。 该工具检测电路设计中存在计数器，识别计数器的一个或多个特殊值，并为计数器创建抽象。 该工具可以自动执行抽象，指导用户配置计数器的适当抽象，或执行自动和手动抽象的组合。 该工具可以进一步容纳相关的计数器。
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3.发明授权Managing formal verification complexity of designs with multiple related counters 有权用多个相关计数器管理设计的正式验证复杂性公开(公告)号：US07647572B1
公开(公告)日：2010-01-12
申请号：US11851330
申请日：2007-09-06
CPC分类号： G06F17/504 , G06F17/5022
摘要： A counter abstraction tool generates an abstraction model for one or more counters in a circuit design for use with a formal verification system. The tool detects the presence of a counter in a circuit design, identifies one or more special values for the counter, and creates an abstraction for the counter. The tool can automatically perform the abstraction, guide a user in configuring the appropriate abstraction for the counter, or perform a combination of automatic and manual abstraction. The tool may further accommodate related counters.
摘要翻译： 计数器抽象工具为电路设计中的一个或多个计数器生成抽象模型，以便与形式验证系统一起使用。 该工具检测电路设计中存在计数器，识别计数器的一个或多个特殊值，并为计数器创建抽象。 该工具可以自动执行抽象，指导用户配置计数器的适当抽象，或执行自动和手动抽象的组合。 该工具可以进一步容纳相关的计数器。
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4.发明授权公开(公告)号：US07159198B1
公开(公告)日：2007-01-02
申请号：US10745993
申请日：2003-12-24
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： The present invention is directed to a system and a method for verifying properties of a circuit model while providing information to help the user manually modify a design analysis region and/or environmental constraints. While conventional systems attempt to substantially automate the entire formal verification process, the present invention iteratively provides information to the user about the cost and effect of changes to the environmental constraints and the analysis region. This information enables the user to weigh the effectiveness and efficiency of one or more modifications to the design analysis area and/or to the environmental constraints (assumptions). The information provided to the user can help a user compare a variety of alternative modifications in order to select the modifications that are efficient and effective. In addition, the information can provide alternatives along with the cost and effect of each alternative to the user who otherwise did not identify these alternatives, thus the invention can help the user by identifying suggestions that the user may not have otherwise considered. The present invention then receives information from the user to modify the design analysis area and/or the environmental constraints and will analyze the design with these modified parameters.
摘要翻译： 本发明涉及一种用于验证电路模型的属性的系统和方法，同时提供信息以帮助用户手动修改设计分析区域和/或环境约束。 虽然常规系统试图使整个形式验证过程大幅自动化，但是本发明向用户反复地提供关于环境约束和分析区域的改变的成本和效果的信息。 该信息使用户能够对设计分析区域和/或环境约束（假设）的一个或多个修改的有效性和效率进行权衡。 提供给用户的信息可以帮助用户比较各种替代修改以选择有效和有效的修改。 此外，该信息可以提供替代方案以及用户的每个备选方案的成本和效果，否则其中没有识别这些替代方案，因此本发明可以通过识别用户可能没有另外考虑的建议来帮助用户。 然后，本发明从用户接收信息以修改设计分析区域和/或环境约束，并将用这些修改的参数分析设计。
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公开(公告)号：US08731894B1
公开(公告)日：2014-05-20
申请号：US13618632
申请日：2012-09-14
申请人： Kathryn Drews Kranen , Chung-Wah Norris Ip , Rajeev Kumar Ranjan , Lawrence Loh , Beth C. Isaksen , Yann Alain Antonioli , Craig Franklin Deaton
发明人： Kathryn Drews Kranen , Chung-Wah Norris Ip , Rajeev Kumar Ranjan , Lawrence Loh , Beth C. Isaksen , Yann Alain Antonioli , Craig Franklin Deaton
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5022
摘要： An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.
摘要翻译： 使用可执行电路设计来产生波形，从中捕获电路的行为。 然后将其行为及其各种组合保存在数据库中，以及关于它们的描述和其他元数据，从而生成电路设计代码的行为指数。 电路设计的行为索引允许用户维护索引行为数据库，跟踪电路设计的可执行描述演变的行为变化，并确定可执行描述如何在不同的项目中重复使用。 当应用于数字设计开发时，它有助于当前的设计和验证工作，以及设计重用。
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公开(公告)号：US08863049B1
公开(公告)日：2014-10-14
申请号：US12961389
申请日：2010-12-06
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： The result of a property based formal verification analysis of a circuit design may include at least one counterexample for each property that is violated, which a user can use to debug the circuit design. To assist the user in this debugging process, a debugging tool applies one or more soft constraints to a counterexample trace that simplify the appearance of the trace when displayed as a waveform. The debugging tool thus facilitates a user's understanding of what parts of the counterexample trace are responsible for the property failure. Also described is a power analysis tool that increases the noise level of a trace for a circuit design in order to facilitate analysis of the circuit design's power characteristics.
摘要翻译： 电路设计的基于属性的形式验证分析的结果可以包括用于违反的每个属性的至少一个反例，用户可以使用该反例来调试电路设计。 为了帮助用户进行此调试过程，调试工具将一个或多个软约束应用于反例样式跟踪，以便在以波形显示时简化跟踪的外观。 因此，调试工具有助于用户了解反例跟踪的哪些部分对属性失败负责。 还描述了功率分析工具，其增加用于电路设计的迹线的噪声水平，以便于电路设计的功率特性的分析。
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公开(公告)号：US08381148B1
公开(公告)日：2013-02-19
申请号：US13404403
申请日：2012-02-24
申请人： Lawrence Loh , Xiaoyang Sun
发明人： Lawrence Loh , Xiaoyang Sun
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A verification system determines proof of the absence of a deadlock condition or other data-transport property in a multi-system SoC using helper assertions derived from a transaction definition. The verification system receives the circuit design information along with a transaction definition for one or more ports of the SoC. Once specified, the transaction definition is instantiated into the full system or subsystem RTL, generating an expanded RTL and a deadlock property. Data flow through the RTL is analyzed to extract helper assertions describing how the data flowed through the RTL. Helper assertions are automatically extracted to aid in the verification of the absence of a deadlock condition. Using the helper assertions, the formal engine applies one or more techniques to formally analyze the circuit design to prove the absence of a deadlock condition.
摘要翻译： 验证系统使用从事务定义导出的辅助断言来确定多系统SoC中没有死锁条件或其他数据传输属性的证据。 验证系统接收电路设计信息以及SoC的一个或多个端口的事务定义。 一旦指定，事务定义被实例化为完整的系统或子系统RTL，生成扩展的RTL和死锁属性。 分析通过RTL的数据流，以提取描述数据流经RTL的帮助者断言。 自动提取助手声明以帮助验证没有死锁条件。 使用助手断言，形式引擎应用一种或多种技术来正式分析电路设计，以证明不存在死锁条件。
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公开(公告)号：US08831925B1
公开(公告)日：2014-09-09
申请号：US12797467
申请日：2010-06-09
申请人： Kathryn Drews Kranen , Chung-Wah Norris Ip , Rajeev Kumar Ranjan , Lawrence Loh , Beth C. Isaksen , Yann Alain Antonioli , Craig Franklin Deaton
发明人： Kathryn Drews Kranen , Chung-Wah Norris Ip , Rajeev Kumar Ranjan , Lawrence Loh , Beth C. Isaksen , Yann Alain Antonioli , Craig Franklin Deaton
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5022
摘要： An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.
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9.发明授权System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit design 有权用于确定和识别在电路设计中由选定信号相关确定的信号的系统和方法公开(公告)号：US07437694B1
公开(公告)日：2008-10-14
申请号：US11063399
申请日：2005-02-22
申请人： Lawrence Loh , Chung-Wah Norris Ip , Soe Myint
发明人： Lawrence Loh , Chung-Wah Norris Ip , Soe Myint
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5022
摘要： A system and method for identifying, for a selected signal, those signals whose value is relevantly determined based upon a value of the selected signal, where a set of signals to be examined is identified as those signals that satisfy one or more of the following criteria: (1) they are RTL load signals of the selected signal, (2) they are RTL load signals that are also in an analysis region, (3) they are RTL load signals within the analysis region that also contribute to a proof target, and/or 4) they are RTL load signals that contribute to the proof target. In one embodiment of the present invention the selected signal at a selected time step relevantly determines a target signal at an associated time step if one of the following items is true: (1) if the value of the selected signal at the selected time step changes (from 0 to 1 or from 1 to 0), the value of the target signal must change, or (2) if the value of the selected signal does not change, the value of the target signal at its associated time step cannot change regardless of how the rest of the inputs to the logic driving the target signal changes. Another embodiment of the present invention, the selected signal at the selected time step relevantly determines a target signal at an associated time step if the value of the selected signal at the selected time step were different then the value of the target signal at the associated time step would be different.
摘要翻译： 一种用于针对所选择的信号识别基于所选信号的值相关地确定其值的那些信号的系统和方法，其中要被检查的一组信号被识别为满足以下标准中的一个或多个的信号 （1）它们是所选信号的RTL负载信号，（2）它们也是分析区域中的RTL负载信号，（3）它们是分析区域内也有助于证明目标的RTL负载信号， 和/或4）它们是有助于证明目标的RTL负载信号。 在本发明的一个实施例中，如果以下项目之一为真，则所选择的时间步骤中所选择的信号相关地确定在相关联的时间步长处的目标信号：（1）如果所选择的时间步长上所选信号的值改变 （从0到1或从1到0），目标信号的值必须改变，或（2）如果所选择的信号的值不改变，则在其相关联的时间步长的目标信号的值不能改变 驱动目标信号的逻辑的其余输入如何变化。 本发明的另一个实施例是，在所选择的时间步长中所选择的信号相关地确定在相关联的时间步长处的目标信号，如果所选择的时间步长的所选择的信号的值与相关时间的目标信号的值不同 一步就会有所不同。
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