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1.发明授权公开(公告)号：US10805064B1
公开(公告)日：2020-10-13
申请号：US16391527
申请日：2019-04-23
申请人： Ciena Corporation
发明人： Sadok Aouini , Naim Ben-Hamida , Ahmad Abdo , Timothy James Creasy , Lukas Jakober , Yalmez M. A. Yazaw , Shahab Oveis Gharan
IPC分类号： H04B10/50 , H04B10/69 , H04L7/033 , H04B10/071 , H04B10/40 , H04B10/25 , H04B10/079
摘要： A system includes an optical transmitter including a transmitter Phase Lock Loop (PLL) circuit; an optical receiver connected to the optical transmitter and including a receiver PLL circuit; and circuitry configured to inject a test stimulus to a clock causing jitter in one of the transmitter PLL circuitry and the receiver PLL circuit, wherein the test stimulus is set for characterizing the jitter tolerance of optical receiver. As well, a circuit that injects SOP transient at the transmitter is included. It is configured to test the tolerance of optical receiver to handle fast change in the SOP state. The optical receiver is configured to determine if the system is operational at a jitter value due to the test stimulus based on compliance to one or more thresholds including any of a target Bit Error Rate, a Forward-Error-Correction (FEC) hit, and a jitter Root Mean Square (RMS).
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公开(公告)号：US20200274537A1
公开(公告)日：2020-08-27
申请号：US16724961
申请日：2019-12-23
申请人： Ciena Corporation
发明人： Sadok Aouini , Naim Ben-Hamida , Timothy James Creasy , Ahmad Abdo , Mahdi Parvizi , Lukas Jakober
摘要： Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.
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公开(公告)号：US10516403B1
公开(公告)日：2019-12-24
申请号：US16287063
申请日：2019-02-27
申请人： Ciena Corporation
发明人： Sadok Aouini , Naim Ben-Hamida , Timothy James Creasy , Ahmad Abdo , Mahdi Parvizi , Lukas Jakober
摘要： Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.
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公开(公告)号：US20230031796A1
公开(公告)日：2023-02-02
申请号：US17383897
申请日：2021-07-23
申请人： Ciena Corporation
IPC分类号： H04B10/07 , H04J3/14 , H04L25/49 , H04L12/861
摘要： Systems and methods include receiving a plurality of symbols that are part of a defined Digital Signal Processing (DSP) frame for coherent optical communication, wherein the DSP frame structure has a messaging channel incorporated therein that includes a subset of the plurality of symbols; capturing multiple samples of the messaging channel; and determining a message in the messaging channel based on analysis of the multiple samples. The method can further include transmitting, in the messaging channel, a reply to the message with the reply being repeated multiple times. The analysis is performed prior to Forward Error Correction (FEC) decoding on the data path.
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公开(公告)号：US11349486B1
公开(公告)日：2022-05-31
申请号：US17434523
申请日：2020-02-25
申请人： Ciena Corporation
发明人： Sadok Aouini , Naim Ben-Hamida , Timothy James Creasy , Ahmad Abdo , Mahdi Parvizi , Lukas Jakober
摘要： Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.
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公开(公告)号：US20220149847A1
公开(公告)日：2022-05-12
申请号：US17434523
申请日：2020-02-25
申请人： Ciena Corporation
发明人： Sadok Aouini , Naim Ben-Hamida , Timothy James Creasy , Ahmad Abdo , Mahdi Parvizi , Lukas Jakober
摘要： Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.
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公开(公告)号：US10985900B1
公开(公告)日：2021-04-20
申请号：US16807356
申请日：2020-03-03
申请人： Ciena Corporation
发明人： Ahmad Abdo , Shahab Oveis Gharan , James Harley , Sadok Aouini , Timothy James Creasy , Naim Ben-Hamida
摘要： Managing clock-data recovery for a modulated signal from a communication channel comprises: receiving the modulated signal and providing one or more analog signals, providing one or more digital input streams from samples of the analog signals, and processing the digital input streams to provide decoded digital data. The processing comprises: determining the decoded digital data based on information modulated over a plurality of frequency elements associated with the modulated signal, based at least in part on transforms of the digital input streams; a clock signal based on clock recovery from the digital input streams; and determining a clock phase error estimate associated with the determined clock signal based at least in part on a sum that includes different weights multiplied by different respective summands corresponding to different sets of frequency elements.
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公开(公告)号：US10749536B1
公开(公告)日：2020-08-18
申请号：US16724961
申请日：2019-12-23
申请人： Ciena Corporation
发明人： Sadok Aouini , Naim Ben-Hamida , Timothy James Creasy , Ahmad Abdo , Mahdi Parvizi , Lukas Jakober
摘要： Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.
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9.发明申请公开(公告)号：US20200344038A1
公开(公告)日：2020-10-29
申请号：US16391527
申请日：2019-04-23
申请人： Ciena Corporation
发明人： Sadok Aouini , Naim Ben-Hamida , Ahmad Abdo , Timothy James Creasy , Lukas Jakober , Yalmez M.A. Yazaw , Shahab Oveis Gharan
IPC分类号： H04L7/033 , H04B10/071 , H04B10/079 , H04B10/25 , H04B10/40
摘要： A system includes an optical transmitter including a transmitter Phase Lock Loop (PLL) circuit; an optical receiver connected to the optical transmitter and including a receiver PLL circuit; and circuitry configured to inject a test stimulus to a clock causing jitter in one of the transmitter PLL circuitry and the receiver PLL circuit, wherein the test stimulus is set for characterizing the jitter tolerance of optical receiver. As well, a circuit that injects SOP transient at the transmitter is included. It is configured to test the tolerance of optical receiver to handle fast change in the SOP state. The optical receiver is configured to determine if the system is operational at a jitter value due to the test stimulus based on compliance to one or more thresholds including any of a target Bit Error Rate, a Forward-Error-Correction (FEC) hit, and a jitter Root Mean Square (RMS).
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