公开(公告)号：US20240154592A1

公开(公告)日：2024-05-09

申请号：US18505734

申请日：2023-11-09

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Andrew J. HOWLETT ,  Michael CHANDLER-PAGE ,  David P. SINGLETON ,  Erich P. ZWYSSIG ,  Craig MCADAM

IPC: H03G3/30 ,  H03F3/04

CPC classification number: H03G3/30 ,  H03F3/04 ,  H03G2201/103

Abstract: An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage, wherein the gain update circuitry comprises level detection circuitry configured to determine a signal level of the first input signal or the first output signal.

公开(公告)号：US20230353111A1

公开(公告)日：2023-11-02

申请号：US17982864

申请日：2022-11-08

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Andrew J. HOWLETT ,  Michael CHANDLER-PAGE ,  David P. SINGLETON ,  Erich P. ZWYSSIG

IPC: H03G3/30 ,  H03F3/04

CPC classification number: H03G3/30 ,  H03F3/04 ,  H03G2201/103

Abstract: An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage.

公开(公告)号：US20230353937A1

公开(公告)日：2023-11-02

申请号：US17983000

申请日：2022-11-08

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Andrew J. HOWLETT ,  Michael CHANDLER-PAGE ,  Lea S. GEORGIEVA

IPC: H04R3/04 ,  H03G3/30

CPC classification number: H04R3/04 ,  H03G3/3005 ,  H04R2430/01

Abstract: Signal processing circuitry configured to receive an input signal and to output a processed output signal, wherein the signal processing circuitry is configured to: receive an indication of a temporal location of a transient in the input signal; and provide, in the processed output signal, a masking signal bridging the temporal location of the transient to mask the transient.

公开(公告)号：US20220229937A1

公开(公告)日：2022-07-21

申请号：US17394014

申请日：2021-08-04

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Michael CHANDLER-PAGE ,  Pradeep SAMINATHAN ,  Jon EKLUND ,  Neil WHYTE ,  José Arnaldo BIANCO FILHO ,  Abhinav SHARMA

IPC: G06F21/71 ,  G06F9/4401

Abstract: An integrated circuit comprises first and second interfaces, an internal addressable space comprising a plurality of address ranges, and a control unit. Each of the first and second interfaces is coupled to the internal addressable space via the control unit. The control unit is configurable in a first state in which the control unit is configured to allow or deny the second interface access to a subset of the plurality of address ranges of the internal addressable space.

公开(公告)号：US20220229784A1

公开(公告)日：2022-07-21

申请号：US17232514

申请日：2021-04-16

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Neil WHYTE ,  Michael CHANDLER-PAGE ,  Pradeep SAMINATHAN ,  Jon EKLUND

IPC: G06F12/14 ,  G06F13/16

Abstract: An integrated circuit comprises first and second interfaces, an internal addressable space comprising a plurality of address ranges, and a control unit. Each of the first and second interfaces is coupled to the internal addressable space via the control unit. The control unit is configurable in a first state in which the control unit is configured to allow or deny the second interface access to a subset of the plurality of address ranges of the internal addressable space.