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公开(公告)号：US4065766A
公开(公告)日：1977-12-27
申请号：US668329
申请日：1976-03-18
CPC分类号： H03M1/508
摘要： A charge transfer analog-to-digital converter is provided wherein a plurality of charge packets is transferred into and out of a charge storage location which includes both linear and nonlinear capacitive components. At the initiation of an analog-to-digital measurement cycle the level of charge in the nonlinear portion of the charge storage location is established at an initial value by comparison with a reference voltage. During the measurement cycle the level of charge in the linear and nonlinear portions of the capacitive charge storage location vary from the initial values thereof as charge is transferred into and out of the charge storage location according to the particular method of analog-to-digital conversion. At the end of the measurement cycle, the level of charge in the nonlinear portion is again established at the initial value thereof so that the net change in charge stored in the nonlinear portion of the charge storage location is zero from the beginning to the end of the measurement cycle.
摘要翻译： 提供了一种电荷转移模数转换器，其中多个电荷包被传送到包括线性和非线性电容分量的电荷存储位置中。 在开始模拟数字测量循环时，通过与参考电压相比，电荷存储位置的非线性部分中的电荷水平以初始值建立。 在测量周期期间，电容性电荷存储单元的线性和非线性部分中的电荷电平根据其初始值而变化，因为根据模数转换的特定方法将电荷转移到电荷存储位置和从电荷存储位置传出 。 在测量周期结束时，非线性部分中的电荷电平在其初始值处再次建立，使得存储在电荷存储位置的非线性部分中的电荷的净变化从零开始到结束 测量周期。
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公开(公告)号：US08242941B2
公开(公告)日：2012-08-14
申请号：US12743960
申请日：2008-11-19
IPC分类号： H03M1/06
CPC分类号： H03M1/0643 , H03M1/0658 , H03M1/0682 , H03M1/0836 , H03M1/508 , H03M1/822
摘要： The invention relates to an A/D converter comprising an input and an output, a D/A converting feedback and a pulse width modulating forward path, the D/A converting feedback comprising at least one feed-back path, the feed-back path establishing a D/A conversion based on at least two D/A conversions subject to uncorrelated errors.The invention further relates to a jitter consequence reducing D/A-converter comprising a jitter-robust intermediate signal established on the basis of a digital input signal.The invention further relates to a method for jitter consequence reduction in a pulse width modulated A/D-converter feedback, comprising establishing at least two D/A-conversions subject to uncorrelated errors, and combining, preferably by summing, said at least two D/A-conversions.
摘要翻译： 本发明涉及一种包括输入和输出，D / A转换反馈和脉宽调制正向通路的A / D转换器，该D / A转换反馈包括至少一个反馈路径，反馈路径 根据不相关错误的至少两个D / A转换建立D / A转换。 本发明还涉及一种抖动结果减少D / A转换器，其包括基于数字输入信号建立的抖动鲁棒中间信号。 本发明还涉及一种用于脉冲宽度调制的A / D转换器反馈的抖动结果减少的方法，包括建立至少两个受到不相关误差的D / A转换，并且优选通过将所述至少两个D / A转换。
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公开(公告)号：US20100245139A1
公开(公告)日：2010-09-30
申请号：US12743960
申请日：2008-11-19
CPC分类号： H03M1/0643 , H03M1/0658 , H03M1/0682 , H03M1/0836 , H03M1/508 , H03M1/822
摘要： The invention relates to an A/D converter comprising an input and an output, a D/A converting feedback and a pulse width modulating forward path, the D/A converting feedback comprising at least one feed-back path, the feed-back path establishing a D/A conversion based on at least two D/A conversions subject to uncorrelated errors.The invention further relates to a jitter consequence reducing D/A-converter comprising a jitter-robust intermediate signal established on the basis of a digital input signal.The invention further relates to a method for jitter consequence reduction in a pulse width modulated A/D-converter feedback, comprising establishing at least two D/A-conversions subject to uncorrelated errors, and combining, preferably by summing, said at least two D/A-conversions.
摘要翻译： 本发明涉及一种包括输入和输出，D / A转换反馈和脉宽调制正向通路的A / D转换器，该D / A转换反馈包括至少一个反馈路径，反馈路径 根据不相关错误的至少两个D / A转换建立D / A转换。 本发明还涉及一种抖动结果减少D / A转换器，其包括基于数字输入信号建立的抖动鲁棒中间信号。 本发明还涉及一种用于脉冲宽度调制的A / D转换器反馈的抖动结果减少的方法，包括建立至少两个受到不相关误差的D / A转换，并且优选通过将所述至少两个D / A转换。
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公开(公告)号：US20080129572A1
公开(公告)日：2008-06-05
申请号：US12030072
申请日：2008-02-12
摘要： The invention relates to at least one self-oscillating loop (SOL) comprising at least one forward path (FP), at least one feedback path (FBP) wherein said at least one forward path (FP) comprises amplitude quantizing means (AQM) combined with time quantizing means (TQM) and outputting at least one time and amplitude quantized signal (OS).According to the invention, a high-speed high-resolution A/D converter may be obtained.
摘要翻译： 本发明涉及包括至少一个正向路径（FP），至少一个反馈路径（FBP）的至少一个自振荡回路（SOL），其中所述至少一个前向路径（FP）包括组合的幅度量化装置（AQM） 具有时间量化装置（TQM）并且输出至少一个时间和幅度量化信号（OS）。 根据本发明，可以获得高速高分辨率A / D转换器。
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公开(公告)号：US20070040721A1
公开(公告)日：2007-02-22
申请号：US10573059
申请日：2003-09-22
IPC分类号： H03M1/12
摘要： The invention relates to at least one self-oscillating loop (SOL) comprising at least one forward path (FP), at least one feedback path (FBP) wherein said at least one forward path (FP) comprises amplitude quantizing means (AQM) combined with time quantizing means (TQM) and outputting at least one time and amplitude quantized signal (OS). According to the invention, a high-speed high-resolution A/D converter may be obtained.
摘要翻译： 本发明涉及包括至少一个正向路径（FP），至少一个反馈路径（FBP）的至少一个自振荡回路（SOL），其中所述至少一个前向路径（FP）包括组合的幅度量化装置（AQM） 具有时间量化装置（TQM）并且输出至少一个时间和幅度量化信号（OS）。 根据本发明，可以获得高速高分辨率A / D转换器。
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公开(公告)号：US11777515B2
公开(公告)日：2023-10-03
申请号：US17241075
申请日：2021-04-27
发明人： Chih-Peng Hsia , Cho-Hsuan Jhang , Su-Wei Lien
CPC分类号： H03M1/508 , H03K5/135 , H03K5/1565 , H03M1/825
摘要： A column analog-to-digital converter and the local counting method is provided. The column analog-to-digital converter includes a plurality of analog-to-digital converters in parallel. Each of the analog-to-digital converters includes a comparator and a counting circuit. The comparator compares the ramp voltage with one of the plurality of column signals to generate a comparator output signal. The counting circuit generates a local clock by means of a voltage-controlled oscillator of the counting circuit according to the base clock and the comparator output signal, counts the base clock and the local clock respectively to generate a first counting output and a second counting output, and combines the first counting output with the second counting output to generate the counting output.
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公开(公告)号：US08525713B2
公开(公告)日：2013-09-03
申请号：US13282158
申请日：2011-10-26
申请人： Ping-Ying Wang
发明人： Ping-Ying Wang
IPC分类号： H03M1/06
CPC分类号： H03M1/508
摘要： A voltage converter for converting an analog input signal into a digital signal is provided. The pulse width of the digital signal is relative to the voltage level of the analog input signal. The voltage converter includes a comparator and a feedback module. After comparing the analog input signal and an analog feedback signal, the comparator generates the digital signal. When the analog input signal is higher than the analog feedback signal, the digital signal has a first voltage level. When the analog input signal is lower than the analog feedback signal, the digital signal has a second voltage level, which is different from the first voltage level. Based on the digital signal, the feedback module adjusts the analog feedback signal toward the analog input signal.
摘要翻译： 提供了一种用于将模拟输入信号转换为数字信号的电压转换器。 数字信号的脉冲宽度相对于模拟输入信号的电压电平。 电压转换器包括比较器和反馈模块。 比较模拟输入信号和模拟反馈信号后，比较器产生数字信号。 当模拟输入信号高于模拟反馈信号时，数字信号具有第一电压电平。 当模拟输入信号低于模拟反馈信号时，数字信号具有与第一电压电平不同的第二电压电平。 基于数字信号，反馈模块将模拟反馈信号调整到模拟输入信号。
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公开(公告)号：US20120098686A1
公开(公告)日：2012-04-26
申请号：US13282158
申请日：2011-10-26
申请人： Ping-Ying WANG
发明人： Ping-Ying WANG
IPC分类号： H03M1/06
CPC分类号： H03M1/508
摘要： A voltage converter for converting an analog input signal into a digital signal is provided. The pulse width of the digital signal is relative to the voltage level of the analog input signal. The voltage converter includes a comparator and a feedback module. After comparing the analog input signal and an analog feedback signal, the comparator generates the digital signal. When the analog input signal is higher than the analog feedback signal, the digital signal has a first voltage level. When the analog input signal is lower than the analog feedback signal, the digital signal has a second voltage level, which is different from the first voltage level. Based on the digital signal, the feedback module adjusts the analog feedback signal toward the analog input signal.
摘要翻译： 提供了一种用于将模拟输入信号转换为数字信号的电压转换器。 数字信号的脉冲宽度相对于模拟输入信号的电压电平。 电压转换器包括比较器和反馈模块。 比较模拟输入信号和模拟反馈信号后，比较器产生数字信号。 当模拟输入信号高于模拟反馈信号时，数字信号具有第一电压电平。 当模拟输入信号低于模拟反馈信号时，数字信号具有与第一电压电平不同的第二电压电平。 基于数字信号，反馈模块将模拟反馈信号调整到模拟输入信号。
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公开(公告)号：US20070085717A1
公开(公告)日：2007-04-19
申请号：US10573053
申请日：2004-09-22
IPC分类号： H03M3/00
摘要： The invention relates to at least one self-oscillating loop (SOL) comprising at least one forward path (FP), at least one feedback path (FBP) wherein said at least one forward path (FP) comprises amplitude quantizing means (AQM) combined with time quantizing means (TQM) and outputting at least one time and amplitude quantized signal (OS). According to the invention, a high-speed high-resolution A/D converter may be obtained.
摘要翻译： 本发明涉及包括至少一个正向路径（FP），至少一个反馈路径（FBP）的至少一个自振荡回路（SOL），其中所述至少一个前向路径（FP）包括组合的幅度量化装置（AQM） 具有时间量化装置（TQM）并且输出至少一个时间和幅度量化信号（OS）。 根据本发明，可以获得高速高分辨率A / D转换器。
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10.发明授权公开(公告)号：US11838029B2
公开(公告)日：2023-12-05
申请号：US17520259
申请日：2021-11-05
IPC分类号： H03M1/12 , G06F13/42 , H03K19/17736 , H03K19/20 , H03M1/50
CPC分类号： H03M1/125 , G06F13/4282 , H03K19/1774 , H03K19/20 , H03M1/123 , H03M1/508
摘要： This invention relates to multichannel signal processing systems using synchronous protocols I2S (Inter-IC Sound Bus) and SPI (Serial Peripheral Bus) for sequenced data exchange, and providing unified synchronization of processed data. The system and method for synchronously multiplexing data streams in the I2S or SPI formats involves transformation of a standard Left/Right Clock (LRCK) sampled pulse signal of the I2S format or a Chip Select (CS) pulse signal of the SPI format into a LRCLt signal comprising a time stamp code and start and end marker codes of the synchronization clock signal, LRCK or CS, respectively. The presence of the marker codes and the time stamp code enables to restore the pulse signal, LRCK or CS, respectively, in the process of data stream program processing and link each discrete sample to the time stamp. The digital stream multiplexing system includes m channel groups for collection of synchronous data in the I2S or SPI synchronous protocol, a clock generator, a host processor and a means of transforming the LRCK or CS signal into the LRCKt signal. The technical effect consists in removal of limitations on a number of fully synchronized data streams in the I2S or SPI formats and, at the same time, simplification of the synchronization system and method and reduction in requirements to hardware resources.
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