公开(公告)号：US11846973B1

公开(公告)日：2023-12-19

申请号：US17982916

申请日：2022-11-08

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Sachin Deo ,  Younes Djadi ,  Nariankadu D. Hemkumar ,  Junsong Li ,  Wai-Shun Shum ,  Franz Weller

IPC: G06F13/10 ,  G06F13/24

CPC classification number: G06F13/24 ,  G06F13/102

Abstract: A multicore processor may include a plurality of cores including at least a first core and a second core, a shared peripheral comprising a plurality of interrupt register banks including at least a first interrupt register bank dedicated to the first core and a second interrupt register bank dedicated to the second core, and a plurality of communications bridges, including at least a first bridge interfaced between the first core and the shared peripheral and at least a second bridge interfaced between the second core and the shared peripheral. The first core may be configured to program the first interrupt register bank via the first bridge to configure the shared peripheral for access by the first core. The second core may be configured to program the second interrupt register bank via the second bridge to configure the shared peripheral for access by the second core.