公开(公告)号：US07043106B2

公开(公告)日：2006-05-09

申请号：US10280492

申请日：2002-10-25

申请人： Lawrence C. West ,  Claes Björkman ,  Dan Maydan ,  Samuel Broydo

发明人： Lawrence C. West ,  Claes Björkman ,  Dan Maydan ,  Samuel Broydo

IPC分类号： G02B6/12

CPC分类号： G02B6/43 ,  G02B6/12 ,  G02B6/12004 ,  G02B6/30 ,  G02B6/4201 ,  G02B6/4214 ,  G02B6/4245 ,  G02B6/4257 ,  G02B6/4274 ,  G02B6/4283

摘要： An optical ready substrate made at least in part of a first semiconductor material and having a front side and a backside, the front side having a top surface that is of sufficient quality to permit microelectronic circuitry to be fabricated thereon using semiconductor fabrication processing techniques. The optical ready substrate includes an optical signal distribution circuit fabricated on the front side of the substrate in a first layer region beneath the top surface of the substrate. The optical signal distribution circuit is made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuitry to be fabricated thereon.

摘要翻译： 至少部分由第一半导体材料制成并且具有前侧和后侧的光学就绪衬底，所述前侧具有足够质量的顶表面，以允许使用半导体制造处理技术在其上制造微电子电路。 光学就绪衬底包括在衬底的顶表面下方的第一层区域中制造在衬底的前侧上的光信号分配电路。 光信号分配电路由互连的半导体光子元件组成，并被设计成向要在其上制造的微电子电路提供信号。

公开(公告)号：US07072534B2

公开(公告)日：2006-07-04

申请号：US10280505

申请日：2002-10-25

申请人： Claes Björkman ,  Lawrence C. West ,  Dan Maydan ,  Samuel Broydo

发明人： Claes Björkman ,  Lawrence C. West ,  Dan Maydan ,  Samuel Broydo

IPC分类号： G02B6/12

CPC分类号： G02B6/12004 ,  G02B6/12 ,  G02B6/30 ,  G02B6/4214 ,  G02B6/4245 ,  G02B6/4257 ,  G02B6/4274 ,  G02B6/4283 ,  G02B6/43

摘要： An article of manufacture comprising an optical ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.

摘要翻译： 一种制品，包括由第一半导体层制成的光学就绪衬底，在第一半导体层的顶部上的绝缘层和在绝缘层的顶部上的第二半导体层，其中第二半导体层具有顶表面，并且是 横向分为包括第一区域和第二区域的两个区域，第一区域的顶表面的质量足以允许在其中形成微电子电路，并且第二区域包括其中形成的光信号分配电路， 光信号分配电路由互连的半导体光子元件组成，并被设计为向要在第二半导体层的第一区域中制造的微电子电路提供信号。

公开(公告)号：US07110629B2

公开(公告)日：2006-09-19

申请号：US10623666

申请日：2003-07-21

申请人： Claes Bjorkman ,  Lawrence C. West ,  Dan Maydan ,  Samuel Broydo

发明人： Claes Bjorkman ,  Lawrence C. West ,  Dan Maydan ,  Samuel Broydo

IPC分类号： G02B6/12

CPC分类号： G02B6/43 ,  G02B6/12 ,  G02B6/12004 ,  G02B6/30 ,  G02B6/4204 ,  G02B6/4214 ,  G02B6/4245 ,  G02B6/4257 ,  G02B6/4274 ,  G02B6/4283 ,  H01L21/84 ,  H01L27/1203

摘要： An article of manufacture comprising an optical-ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.

摘要翻译： 一种制造方法，包括由第一半导体层制成的光学就绪衬底，在第一半导体层的顶部上的绝缘层和在绝缘层的顶部上的第二半导体层，其中第二半导体层具有顶表面和 横向分为包括第一区域和第二区域的两个区域，第一区域的顶表面具有足以允许在其中形成微电子电路的质量，并且第二区域包括其中形成的光信号分配电路， 所述光信号分配电路由互连的半导体光子元件组成并且被设计成向要在第二半导体层的第一区域中制造的微电子电路提供信号。

公开(公告)号：US20070080414A1

公开(公告)日：2007-04-12

申请号：US11522856

申请日：2006-09-18

申请人： Claes Bjorkman ,  Lawrence West ,  Dan Maydan ,  Samuel Broydo

发明人： Claes Bjorkman ,  Lawrence West ,  Dan Maydan ,  Samuel Broydo

IPC分类号： H01L31/0232

CPC分类号： G02B6/43 ,  G02B6/12 ,  G02B6/12004 ,  G02B6/30 ,  G02B6/4204 ,  G02B6/4214 ,  G02B6/4245 ,  G02B6/4257 ,  G02B6/4274 ,  G02B6/4283 ,  H01L21/84 ,  H01L27/1203

摘要： An article of manufacture comprising an optical-ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.

摘要翻译： 一种制造方法，包括由第一半导体层制成的光学就绪衬底，在第一半导体层的顶部上的绝缘层和在绝缘层的顶部上的第二半导体层，其中第二半导体层具有顶表面和 横向分为包括第一区域和第二区域的两个区域，第一区域的顶表面具有足以允许在其中形成微电子电路的质量，并且第二区域包括其中形成的光信号分配电路， 所述光信号分配电路由互连的半导体光子元件组成并且被设计成向要在第二半导体层的第一区域中制造的微电子电路提供信号。

公开(公告)号：US20050072979A1

公开(公告)日：2005-04-07

申请号：US10623665

申请日：2003-07-21

申请人： Lawrence West ,  Dan Maydan ,  Samuel Broydo ,  Claes Bjorkman

发明人： Lawrence West ,  Dan Maydan ,  Samuel Broydo ,  Claes Bjorkman

IPC分类号： G02B6/12 ,  G02B6/30 ,  G02B6/42 ,  G02B6/43 ,  H01L27/15

CPC分类号： G02B6/12 ,  G02B6/12004 ,  G02B6/30 ,  G02B6/4201 ,  G02B6/4214 ,  G02B6/4245 ,  G02B6/4257 ,  G02B6/4274 ,  G02B6/4283 ,  G02B6/43

摘要： An optical-ready substrate made at least in part of a first semiconductor material and having a front side and a backside, the front side having a top surface that is of sufficient quality to permit microelectronic circuitry to be fabricated thereon using semiconductor fabrication processing techniques. The optical-ready substrate includes an optical signal distribution circuit fabricated on the front side of the substrate in a first layer region beneath the top surface of the substrate. The optical signal distribution circuit is made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuitry to be fabricated thereon.

摘要翻译： 至少部分由第一半导体材料制成且具有正面和背面的光学就绪衬底，其前侧具有足够质量的顶表面，以允许使用半导体制造处理技术在其上制造微电子电路。 光学就绪衬底包括在衬底的顶表面下方的第一层区域中制造在衬底的前侧上的光信号分配电路。 光信号分配电路由互连的半导体光子元件组成，并被设计成向要在其上制造的微电子电路提供信号。

公开(公告)号：US06514671B1

公开(公告)日：2003-02-04

申请号：US09675989

申请日：2000-09-29

申请人： Suketu A. Parikh ,  Mehul B. Naik ,  Samuel Broydo ,  H. Peter W. Hey

发明人： Suketu A. Parikh ,  Mehul B. Naik ,  Samuel Broydo ,  H. Peter W. Hey

IPC分类号： G03C500

CPC分类号： H01L21/76808 ,  H01L23/485 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures (332 and 334) are formed in consecutive dielectric layers (314 and 316) having dissimilar etching characteristics. The present invention also provides for such methods and devices wherein these dielectric layers have different dielectric constants. Additional embodiments of the present invention include the use of single layer masks, such as silicon-based photosensitive materials which form a hard mask (622) upon exposure to radiation. In additional embodiments, manufacturing systems (710) are provided for fabricating IC structures. These systems include a controller (700) which is adapted for interacting with a plurality of fabrication stations (720, 722, 724, 726, 728 and 730).

摘要翻译： 本发明提供集成电路制造方法和装置，其中双镶嵌结构（332和334）形成在具有不同蚀刻特性的连续介电层（314和316）中。 本发明还提供了这样的方法和装置，其中这些介电层具有不同的介电常数。 本发明的另外的实施方案包括使用单层掩模，例如在暴露于辐射时形成硬掩模（622）的硅基感光材料。 在另外的实施例中，制造系统（710）用于制造IC结构。 这些系统包括适于与多个制造站（720,722,724,726,728和730）相互作用的控制器（700）。

公开(公告)号：US5646814A

公开(公告)日：1997-07-08

申请号：US276010

申请日：1994-07-15

申请人： Shamouil Shamouilian ,  Samuel Broydo ,  Manoocher Birang

发明人： Shamouil Shamouilian ,  Samuel Broydo ,  Manoocher Birang

IPC分类号： B23Q3/15 ,  H01L21/683 ,  H02N13/00

CPC分类号： H01L21/6875 ,  H01L21/6831 ,  H01L21/6833

摘要： A multi-electrode electrostatic chuck (20) for holding a substrate (42) such as a silicon wafer during processing is described. The electrostatic chuck (20) comprises (i) a first electrode (22), (ii) a second electrode (24), and (iii) an insulator (26) having a lower portion (26a), a middle portion (26b) and an upper portion (26c). The lower portion (26a) of the insulator (26) is below the first electrode (22) and has a bottom surface (28) suitable for resting the chuck (20) on a support (44) in a process chamber (41). The middle portion (26b) of the insulator (26) lies between the first and second electrodes (22), (24). The upper portion (26c) of the insulator (26) is on the second electrode (24), and has a top surface (30) suitable for holding a substrate (42). The first and second electrodes (22, 24) can have a unipolar or bipolar configurations. In operation, the chuck (20) is placed on a support (44) in a process chamber (41) so that the bottom surface (28) of the chuck (20) rests on the support (44). A substrate (42) is placed on the top surface (30) of the chuck (20). When the first electrode (22) of the chuck (20) is electrically biased with respect to the support (44), a first electrostatic force holds the chuck (20) onto the support (44). When the second electrode (24) of the chuck (20) is electrically biased with respect to the substrate (42) placed on the chuck (20), a second electrostatic force holds the substrate (42) to the chuck (20).

摘要翻译： 描述了用于在处理期间保持硅晶片等基板（42）的多电极静电卡盘（20）。 静电卡盘（20）包括（i）第一电极（22），（ii）第二电极（24）和（iii）具有下部分（26a）的绝缘体（26），中间部分（26b） 和上部（26c）。 绝缘体（26）的下部（26a）位于第一电极（22）的下面，并且具有适于将卡盘（20）放置在处理室（41）中的支撑件（44）上的底表面（28）。 绝缘体（26）的中间部分（26b）位于第一和第二电极（22），（24）之间。 绝缘体（26）的上部（26c）在第二电极（24）上，并且具有适于保持基板（42）的顶表面（30）。 第一和第二电极（22,24）可以具有单极或双极结构。 在操作中，卡盘（20）被放置在处理室（41）中的支撑件（44）上，使得卡盘（20）的底表面（28）搁置在支撑件（44）上。 基板（42）被放置在卡盘（20）的顶表面（30）上。 当卡盘（20）的第一电极（22）相对于支撑件（44）被电偏置时，第一静电力将卡盘（20）保持在支撑件（44）上。 当卡盘（20）的第二电极（24）相对于放置在卡盘（20）上的基板（42）电气偏置时，第二静电力将基板（42）保持在卡盘（20）上。

公开(公告)号：US06548396B2

公开(公告)日：2003-04-15

申请号：US09874874

申请日：2001-06-05

申请人： Mehul Naik ,  Samuel Broydo

发明人： Mehul Naik ,  Samuel Broydo

IPC分类号： H01L214763

CPC分类号： H01L21/76808

摘要： A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.

公开(公告)号：US5689133A

公开(公告)日：1997-11-18

申请号：US709611

申请日：1996-09-09

申请人： Sheau-Suey Li ,  Randy T. Ong ,  Samuel Broydo ,  Khue Duong

发明人： Sheau-Suey Li ,  Randy T. Ong ,  Samuel Broydo ,  Khue Duong

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0251 ,  H01L27/0259

摘要： An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp. Certain P-type channel stop implants are positioned away from nearby N-regions to increase breakdown voltage.

摘要翻译： ESD保护电路将分离双极晶体管与晶体管布局相结合，对ESD事件表现出非常高的耐受性。 分离双极晶体管在许多段之间划分电流，并防止通常导致ESD故障的电流异常。 公开了几种分裂结构，每个组合电阻器与每个段串联以分布电流均匀。 晶体管利用闪回效应来增加载流能力。 布局位置金属触点远离能量消耗最高的区域。 布局还允许高电流通过ESD保护结构消散，而不是通过电路设备（如输出驱动器）或通过非高电流设计的寄生双极型晶体管来消除。 通过在注入轻掺杂和重掺杂水平的N区中使用高扩散性磷来避免电子密度的急剧变化。 关键角是圆形而不是锋利的。 某些P型通道停止植入物远离附近的N区域以增加击穿电压。

公开(公告)号：US5477414A

公开(公告)日：1995-12-19

申请号：US58189

申请日：1993-05-03

申请人： Sheau-Suey Li ,  Randy T. Ong ,  Samuel Broydo ,  Khue Duong

发明人： Sheau-Suey Li ,  Randy T. Ong ,  Samuel Broydo ,  Khue Duong

IPC分类号： H01L27/02 ,  H02H9/04

CPC分类号： H01L27/0251 ,  H01L27/0259

摘要： An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp. Certain P-type channel stop implants are positioned away from nearby N-regions to increase breakdown voltage.

摘要翻译： ESD保护电路将分离双极晶体管与晶体管布局相结合，对ESD事件表现出非常高的耐受性。 分离双极晶体管在许多段之间划分电流，并防止通常导致ESD故障的电流异常。 公开了几种分裂结构，每个组合电阻器与每个段串联以分布电流均匀。 晶体管利用闪回效应来增加载流能力。 布局位置金属触点远离能量消耗最高的区域。 布局还允许高电流通过ESD保护结构消散，而不是通过电路设备（如输出驱动器）或通过非高电流设计的寄生双极型晶体管来消除。 通过在注入轻掺杂和重掺杂水平的N区中使用高扩散性磷来避免电子密度的急剧变化。 关键角是圆形而不是锋利的。 某些P型通道停止植入物远离附近的N区域以增加击穿电压。