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    System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position
    1.
    发明申请
    System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position 失效
    网络处理器中的系统方法结构，通过最后一个标志位指示帧分组的最后数据缓冲区，处于第一或第二位置

    公开(公告)号：US20060101172A1

    公开(公告)日：2006-05-11

    申请号：US11320277

    申请日：2005-12-27

    申请人： Claude Basso ,  Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    IPC分类号： G06F5/00

    CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

    摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

    摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

    Flexible control block format for frame description and management
    2.
    发明申请
    Flexible control block format for frame description and management 失效
    灵活的控制块格式，用于帧描述和管理

    公开(公告)号：US20060215677A1

    公开(公告)日：2006-09-28

    申请号：US11091245

    申请日：2005-03-28

    申请人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Joseph Logan ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Joseph Logan ,  Fabrice Verplanken

    IPC分类号： H04L12/26 ,  H04L12/56

    CPC分类号： H04L12/5601 ,  H04L49/90 ,  H04L2012/5642 ,  H04L2012/5652 ,  H04L2012/5658 ,  H04L2012/5681

    摘要： A communication network used to link information handling systems together utilizes a switching network to transmit data among senders and receivers. Each individual packet of data is described and controlled by an FCB. The bandwidth associated with the storing and distribution of data is optimized by chaining the data packets in different types of queues, or operating without chaining outside a queue. When a frame is in an output queue, the third word contains an RFCBA for egress of the frame to a line port, and an MCID for ingress from an output queue to a switch port. The RFCBA and the MCID have multicast capabilities. The format does not require a third word when a frame is in an input queue.

    摘要翻译： 用于将信息处理系统链接在一起的通信网络利用交换网络在发送者和接收者之间传送数据。 每个单独的数据包由FCB描述和控制。 与存储和分发数据相关联的带宽通过将数据分组链接在不同类型的队列中进行优化，或者在不在队列外链接的情况下运行。 当帧位于输出队列中时，第三个字包含用于将帧从线路端口排出的RFCBA，以及用于从输出队列进入交换机端口的MCID。 RFCBA和MCID具有多播功能。 当帧在输入队列中时，格式不需要第三个字。

    Systems and methods for weighted best effort scheduling
    4.
    发明申请
    Systems and methods for weighted best effort scheduling 失效
    加权最佳努力调度的系统和方法

    公开(公告)号：US20060233177A1

    公开(公告)日：2006-10-19

    申请号：US11108485

    申请日：2005-04-18

    申请人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

    IPC分类号： H04L12/56 ,  H04L12/54

    CPC分类号： H04L47/568 ,  H04L45/00 ,  H04L45/60 ,  H04L47/50 ,  H04L47/527

    摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a three-entry calendar structure provides for weighted best effort scheduling. Each of a plurality different flows has an associated schedule control block. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a weight according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its weight, the schedule control block is temporarily removed from further scheduling.

    摘要翻译： 公开了一种用于在网络处理器中调度数据分组的系统和方法。 实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。 在一个实施例中，三入口日历结构提供加权最佳努力调度。 多个不同的流中的每一个具有相关的进度控制块。 计划控制块作为链表存储在先进先出缓冲区中。 通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。 每个调度控制块具有计数器，并根据相应分组所属的流的带宽优先级分配权重。 每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。 当调度控制块的递增计数器等于其权重时，调度控制块暂时从进一步调度中移除。

    Method and device of multicasting data in a communications system
    6.
    发明授权
    Method and device of multicasting data in a communications system 失效
    在通信系统中组播数据的方法和设备

    公开(公告)号：US6038592A

    公开(公告)日：2000-03-14

    申请号：US635048

    申请日：1996-04-19

    申请人： Fabrice Verplanken ,  Claude Basso ,  Didier Giroir ,  Jean Calvignac ,  Claude Galand

    发明人： Fabrice Verplanken ,  Claude Basso ,  Didier Giroir ,  Jean Calvignac ,  Claude Galand

    IPC分类号： G06F13/00 ,  G06F15/16 ,  G06F15/177 ,  H04L12/18

    CPC分类号： H04L12/18

    摘要： An apparatus and method for multicasting messages stored in data buffers of a data storage. Each message is composed of data stored in a plurality of the data buffers. Each data buffer is controlled and mapped to a unique direct control block (DCB) which stores information characterizing the data buffer. By chaining the DCBs variable length, messages can be generated. Indirect control blocks (ICB) stores information characterizing the data or messages duplicated and points to a DCB. A field in the DCB carries a count representing the number of times the message is to be duplicated.

    摘要翻译： 一种用于组播存储在数据存储器的数据缓冲器中的消息的装置和方法。 每个消息由存储在多个数据缓冲器中的数据组成。 每个数据缓冲器被控制并映射到唯一的直接控制块（DCB），其存储表征数据缓冲器的信息。 通过链接DCBs可变长度，可以生成消息。 间接控制块（ICB）存储表征复制的数据或消息的信息，并指向DCB。 DCB中的字段表示消息被复制的次数。

    Method and system for in-site and on-line reprogramming of hardware logics with remote loading in a network device
    7.
    发明授权
    Method and system for in-site and on-line reprogramming of hardware logics with remote loading in a network device 失效
    在网络设备中进行远程加载的硬件逻辑的现场和在线重新编程的方法和系统

    公开(公告)号：US5794033A

    公开(公告)日：1998-08-11

    申请号：US547635

    申请日：1995-10-24

    申请人： Jeane-Paul Aldebert ,  Claude Basso ,  Jean Calvignac ,  Paul Chemla ,  Daniel Orsatti ,  Fabrice Verplanken ,  Jean-Claude Zunino

    发明人： Jeane-Paul Aldebert ,  Claude Basso ,  Jean Calvignac ,  Paul Chemla ,  Daniel Orsatti ,  Fabrice Verplanken ,  Jean-Claude Zunino

    IPC分类号： G06F13/38 ,  H03K19/177

    CPC分类号： G06F13/4256

    摘要： The invention discloses a method and an apparatus for in-line and on-site updating of Field Programmable Gate Arrays with remote loaded configuration data files. Flash EEPROMs which are used because of their non-volatile memories and their high density, are storing more than one configuration data file. The memories are divided in more than one part, each part of the memory for storing one configuration data file. One part of the memory also contains a flag identifying the currently loaded configuration data file. The Flash EPROM's bits being set to one same binary value before any writing operation, including the update of the configuration data file containing the flag. The setting of the bits to said binary value always identifies a valid other configuration data file in order to insure a correct re-loading of the FPGAs in case of reception of an unexpected event leading to an initialization.

    摘要翻译： 本发明公开了一种用于使用远程加载的配置数据文件进行现场可编程门阵列的在线和现场更新的方法和装置。 由于其非易失性存储器及其高密度使用的闪存EEPROM存储多个配置数据文件。 存储器分为多个部分，存储器的每个部分用于存储一个配置数据文件。 存储器的一部分还包含标识当前加载的配置数据文件的标志。 闪存EPROM的位在任何写入操作之前被设置为相同的二进制值，包括更新包含该标志的配置数据文件。 对所述二进制值的位的设置总是标识有效的其他配置数据文件，以便在接收到导致初始化的意外事件的情况下确保正确地重新加载FPGA。