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    Effective Work Function Modulation by Metal Thickness and Nitrogen Ratio for a Last Approach CMOS Gate
    1.
    发明申请
    Effective Work Function Modulation by Metal Thickness and Nitrogen Ratio for a Last Approach CMOS Gate 审中-公开
    通过金属厚度和氮比的有效工作功能调制最终方法CMOS门

    公开(公告)号：US20130087856A1

    公开(公告)日：2013-04-11

    申请号：US13253430

    申请日：2011-10-05

    申请人： Claude Ortolland ,  Unoh Kwon ,  Kota V.R.M. Murali ,  Edward J. Nowak ,  Rajan Kumar Pandey

    发明人： Claude Ortolland ,  Unoh Kwon ,  Kota V.R.M. Murali ,  Edward J. Nowak ,  Rajan Kumar Pandey

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/66545

    摘要： A CMOS structure is formed on a semiconductor substrate that includes first and second regions having an nFET and a pFET respectively formed thereon. Each nFET and pFET device is provided with a gate, a source and drain, and a channel formed on the substrate. A high permittivity dielectric layer formed on top of the channel is superimposed to the permittivity dielectric layer. The pFET gate includes a thick metal nitride alloy layer or rich metal nitride alloy or carbon metal nitride layer that provides a controlled WF. Superimposed to the permittivity dielectric layer, the nFET gate is provided with a thin metal nitride alloy layer, enabling to control the WF. A metal deposition is formed on top of the respective nitride layers. The gate last approach characterized by having a high thermal budget smaller than 500° C. used for post metal deposition, following the dopant activation anneal.

    摘要翻译： 在包括分别在其上形成有nFET和pFET的第一和第二区域的半导体衬底上形成CMOS结构。 每个nFET和pFET器件设置有栅极，源极和漏极以及形成在衬底上的沟道。 形成在通道顶部的高介电常数介电层叠加到介电常数介电层上。 pFET栅极包括提供受控WF的厚金属氮化物合金层或富金属氮化物合金或碳金属氮化物层。 与介电常数介电层叠加，nFET栅极设置有薄的金属氮化物合金层，能够控制WF。 在各个氮化物层的顶部上形成金属沉积。 门最后一种方法的特征在于，在掺杂剂激活退火之后，具有小于500℃的高热预算用于后金属沉积。

    STRUCTURE AND FABRICATION METHOD OF TUNNEL FIELD EFFECT TRANSISTOR WITH INCREASED DRIVE CURRENT AND REDUCED GATE INDUCED DRAIN LEAKAGE (GIDL)
    2.
    发明申请
    STRUCTURE AND FABRICATION METHOD OF TUNNEL FIELD EFFECT TRANSISTOR WITH INCREASED DRIVE CURRENT AND REDUCED GATE INDUCED DRAIN LEAKAGE (GIDL) 有权
    隧道场效应晶体管的结构和制造方法具有增加的驱动电流和降低的栅极诱发的漏极泄漏（GIDL）

    公开(公告)号：US20120256248A1

    公开(公告)日：2012-10-11

    申请号：US13082867

    申请日：2011-04-08

    申请人： Mohit Bajaj ,  Kota V.R.M. Murali ,  Edward J. Nowak ,  Rajan K. Pandey

    发明人： Mohit Bajaj ,  Kota V.R.M. Murali ,  Edward J. Nowak ,  Rajan K. Pandey

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L29/7391 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/66356

    摘要： Gate induced drain leakage in a tunnel field effect transistor is reduced while drive current is increased by orienting adjacent semiconductor bodies, based on their respective crystal orientations or axes, to optimize band-to-band tunneling at junctions. Maximizing band-to-band tunneling at a source-channel junction increases drive current, while minimizing band-to-band tunneling at a channel-drain junction decreases GIDL. GIDL can be reduced by an order of magnitude in an embodiment. Power consumption for a given frequency can also be reduced by an order of magnitude.

    摘要翻译： 通过基于它们各自的晶体取向或轴定向相邻的半导体本体来增加隧道场效应晶体管中的栅极感应漏极泄漏，同时通过使相邻的半导体本体取向来提高驱动电流，以优化在结处的带 - 带隧穿。 在源极 - 沟道结上最大化带 - 带隧穿可增加驱动电流，同时最小化通道 - 漏极结上的带 - 带隧穿可以减小GIDL。 在实施例中，GIDL可以减少一个数量级。 给定频率的功耗也可以减少一个数量级。