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    CMOS-microprocessor chip and package anti-resonance apparatus
    1.
    发明授权
    CMOS-microprocessor chip and package anti-resonance apparatus 有权
    CMOS微处理器芯片和封装反谐振装置

    公开(公告)号：US06483341B2

    公开(公告)日：2002-11-19

    申请号：US09754564

    申请日：2001-01-04

    申请人： Claude R. Gauthier ,  Tyler J. Thorp ,  Richard L. Wheeler ,  Brian Amick

    发明人： Claude R. Gauthier ,  Tyler J. Thorp ,  Richard L. Wheeler ,  Brian Amick

    IPC分类号： H03K1716

    CPC分类号： H02M3/00 ,  H02M1/44 ,  H02M3/07

    摘要： An apparatus for regulating resonance in a micro-chip has been developed. The method includes connecting a de-coupled capacitance across the supply and ground voltages, and connecting a band-pass shunt regulator that is in parallel to the capacitor across the supply and ground voltages. The regulator will short circuit the supply and ground voltages at a pre-determined frequency to reduce the resonance effect on the micro-chip.

    摘要翻译： 已经开发了用于调节微芯片中的共振的装置。 该方法包括在电源和接地电压之间连接去耦合电容，以及在电源和接地电压之间连接与电容器并联的带通分流调节器。 调节器将以预定频率将电源和接地电压短路，以减少对微芯片的共振效应。

    CMOS-microprocessor chip and package anti-resonance method
    2.
    发明授权
    CMOS-microprocessor chip and package anti-resonance method 有权
    CMOS微处理器芯片和封装反共振方法

    公开(公告)号：US06456107B1

    公开(公告)日：2002-09-24

    申请号：US09754573

    申请日：2001-01-04

    申请人： Claude R. Gauthier ,  Tyler J. Thorp ,  Richard L. Wheeler ,  Brian Amick

    发明人： Claude R. Gauthier ,  Tyler J. Thorp ,  Richard L. Wheeler ,  Brian Amick

    IPC分类号： H03K19003

    CPC分类号： H02M3/00 ,  H02M1/44 ,  H02M3/07

    摘要： A method for regulating resonance in a micro-chip has been developed. The circuit includes an on-chip de-coupled capacitor that is shunted across the supply and ground voltages, and a band-pass shunt regulator that is in parallel to the capacitor across the supply and ground voltages. The regulator will short circuit the supply and ground voltages at a pre-determined frequency to reduce the resonance effect on the micro-chip.

    摘要翻译： 已经开发了用于调节微芯片中的共振的方法。 该电路包括一个在电源和接地电压上分流的片上去耦合电容器，以及一个在电源和接地电压上与电容并联的带通分流调节器。 调节器将以预定频率将电源和接地电压短路，以减少对微芯片的共振效应。

    Deskewing global clock skew using localized DLLs
    6.
    发明授权
    Deskewing global clock skew using localized DLLs 有权
    使用本地化DLL来消除全局时钟偏移

    公开(公告)号：US06686785B2

    公开(公告)日：2004-02-03

    申请号：US09975359

    申请日：2001-10-11

    申请人： Dean Liu ,  Tyler J. Thorp ,  Pradeep R. Trivedi ,  Gin S. Yee ,  Claude R. Gauthier

    发明人： Dean Liu ,  Tyler J. Thorp ,  Pradeep R. Trivedi ,  Gin S. Yee ,  Claude R. Gauthier

    IPC分类号： H03L706

    CPC分类号： H03L7/07 ,  G06F1/10 ,  H03L7/0814

    摘要： An integrated circuit has a plurality of sections, each having a phase detector and a control delay circuit. The phase detector, in response to a phase difference between a reference clock signal and a feedback signal from a portion of a clock grid, controls the delay of its associated clock delay circuit, which, in turn, outputs to the portion of the clock grid. The feedback signal to the phase detector may be connected to an output of a DLL or another portion of the clock grid controlled by a clock delay circuit not associated with the phase detector. Such an arrangement on the integrated circuit leads to clock grid skew reduction.

    摘要翻译： 集成电路具有多个部分，每个部分具有相位检测器和控制延迟电路。 相位检测器响应于参考时钟信号和来自时钟网格的一部分的反馈信号之间的相位差来控制其关联的时钟延迟电路的延迟，其又输出到时钟网格的一部分 。 到相位检测器的反馈信号可以连接到DLL或由与相位检测器不相关的时钟延迟电路控制的时钟网格的另一部分的输出。 集成电路上的这种布置导致时钟网格偏移减少。

    Method and apparatus to store delay locked loop biasing parameters
    9.
    发明授权
    Method and apparatus to store delay locked loop biasing parameters 有权
    存储延迟锁定环偏置参数的方法和装置

    公开(公告)号：US07251305B2

    公开(公告)日：2007-07-31

    申请号：US10147838

    申请日：2002-05-17

    申请人： Claude R. Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

    发明人： Claude R. Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

    IPC分类号： H03D3/24

    CPC分类号： H03L7/0812

    摘要： A calibration and adjustment system for post-fabrication control of a delay locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the delay locked loop.

    摘要翻译： 提供了一种用于延迟锁定环偏置发生器的后制造控制的校准和调整系统。 校准和调整系统包括可操作地连接到偏置发生器的调节电路，其中调节电路是可控制的，以便于修正偏置发生器的电压输出。 由偏置发生器输出的电压的这种控制允许设计者在制造延迟锁定环路之后实现期望的延迟锁定环路性能特性。 可以存储和随后读取偏置 - 发生器输出中期望的调节量的代表值来调整延迟锁定环。