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1.发明授权
公开(公告)号：US5572156A
公开(公告)日：1996-11-05
申请号：US529883
申请日：1995-09-18
CPC分类号： H03K3/356113 , H03K17/063 , H03K17/161 , H03K17/687
摘要： A control circuit for a power transistor, connected between two supply terminals in series with a load. The control circuit comprises a control logic circuit which produces a signal at two levels with respect to a reference terminal, a level shifter connected between the control circuit and the power transistor, which produces a signal at two levels relative to the node between the power transistor and the load. The level shifter comprises a flip-flop the output of which controls the power transistor, and an electronic switch, for example a MOSFET transistor, connected between the "set" input of the flip-flop and the node and controlled by the "reset" input of the flip-flop in such a way as to be closed when the "reset" input is greater, by a predetermined value, than that of the node. The electronic switch prevents the parasitic current flowing through the set and reset inputs from erroneously switching the power transistor.
摘要翻译： 用于功率晶体管的控制电路，连接在与负载串联的两个电源端子之间。 该控制电路包括控制逻辑电路，该控制逻辑电路相对于参考端产生两个电平的信号，连接在控制电路和功率晶体管之间的电平转换器，其产生相对于功率晶体管 和负载。 电平移位器包括其输出端控制功率晶体管的触发器和连接在触发器的“设置”输入和节点之间并由“复位”控制的电子开关，例如MOSFET晶体管， 触发器的输入以当“复位”输入比节点的输入大一预定值时被关闭。 电子开关防止流过设定和复位输入的寄生电流错误地切换功率晶体管。
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公开(公告)号：US5883547A
公开(公告)日：1999-03-16
申请号：US644449
申请日：1996-05-13
IPC分类号： G01R19/165 , H01L21/8234 , H01L27/088 , H02J1/00 , H03K17/06 , H03K17/0814 , H02M7/162
CPC分类号： H03K17/08142 , H03K17/063
摘要： A charging circuit for a bootstrap capacitance employing an integrated LDMOS transistor and including a circuital device for preventing the turning on a parasitic transistors of the integrated LDMOS structure during transients that comprises a plurality of directly biased junctions (D1, D2, . . . , Dn) connected in series between a source and a body of the LDMOS transistor structure and at least a current generator, tied to ground potential, coupled between said body and ground, has at least one switch (INT1) between said source and a first junction (D1) of said plurality of junctions and a limiting resistance (R) connected between the body and the current generator (GEN). The switch (INT1) is kept open during a charging phase of the bootstrap capacitance (Cboot) and is closed when the charge voltage (Vboot) of the bootstrap capacitance reaches a preset threshold. Moreover, the body voltage (VB) is prevented from exceeding the source voltage (VS) plus a Vbe, by controlling a discharge path (T2) with a control stage (T1, R1) in response to a drop of the voltage on the limiting resistance (R). This body voltage control circuit is enabled by a second switch (INT2) driven in phase with the first switch (INT1).
摘要翻译： 一种用于使用集成LDMOS晶体管的自举电容的充电电路，并且包括用于在包括多个直接偏置的结（D1，D2，...，Dn）的瞬变期间阻止集成LDMOS结构的寄生晶体管的导通的电路装置 ）串联连接在LDMOS晶体管结构的源极和主体之间，并且至少连接在所述主体和地之间的接地电位的电流发生器在所述源和第一结之间具有至少一个开关（INT1） D1）和连接在主体和电流发生器（GEN）之间的限制电阻（R）。 开关（INT1）在自举电容（Cboot）的充电阶段保持打开，当自举电容的充电电压（Vboot）达到预设阈值时，开关闭合。 此外，通过响应于限制电压的下降控制具有控制级（T1，R1）的放电路径（T2），防止体电压（VB）超过源极电压（VS）加上Vbe 电阻（R）。 该体电压控制电路由与第一开关（INT1）同相驱动的第二开关（INT2）使能。
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公开(公告)号：US5825138A
公开(公告)日：1998-10-20
申请号：US721437
申请日：1996-09-27
IPC分类号： H05B41/295 , G05F1/00
CPC分类号： H05B41/295
摘要： The need of implementing a second local oscillator in addition to the drive oscillator, for timing the different phases of the starting process of a half-bridge or bridge stage driving an external load, such as a fluorescent lamp, is avoided by employing a timing counter to count the number of oscillations produced by the drive oscillator, and a digital-to-analog converter for controlling the frequency of oscillation of the drive oscillator.
摘要翻译： 除了驱动振荡器之外实现第二本地振荡器的需要，用于定时驱动诸如荧光灯的外部负载的半桥或桥接台的启动过程的不同阶段，通过采用定时计数器 以计数由驱动振荡器产生的振荡的数量，以及用于控制驱动振荡器的振荡频率的数模转换器。
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4.发明授权Integrated control circuit with a level shifter for switching an electronic switch 失效具有用于切换电子开关的电平转换器的集成控制电路
公开(公告)号：US5552731A
公开(公告)日：1996-09-03
申请号：US529882
申请日：1995-09-18
IPC分类号： H02P7/29 , H03K17/16 , H03K17/687 , H03K3/00
CPC分类号： H03K17/687 , H03K17/161
摘要： A circuit for controlling a power transistor connected in series with a load. The circuit comprises a control logic circuit which produces a signal at two levels with respect to a reference terminal, a level shifter connected between the control circuit and the power transistor, and which produces a signal at two levels referred to the node between the power transistor and the load. The level shifter includes a flip-flop the output of which controls the power transistor as well as two transistors driven by the control logic circuit to switch alternately and provide switching signals on the "set" and "reset" inputs of the flip-flop via two resistors. Two parasitic current generators inject current into the two resistors during the phase in which the power transistor is cut off. To prevent this current from causing unwanted switching of the flip-flop, a resistor connected to the "set" terminal of the flip-flop has a lower resistance than that of the other resistor.
摘要翻译： 用于控制与负载串联连接的功率晶体管的电路。 该电路包括控制逻辑电路，该控制逻辑电路相对于参考端产生两个电平的信号，连接在控制电路和功率晶体管之间的电平转换器，并且其产生两个电平的信号，所述两个电平参考功率晶体管 和负载。 电平移位器包括触发器，其输出控制功率晶体管以及由控制逻辑电路驱动的两个晶体管交替切换，并在触发器的“设置”和“复位”输入端经由 两个电阻。 在功率晶体管截止的阶段，两个寄生电流发生器将电流注入到两个电阻中。 为了防止该电流引起触发器的不期望的切换，连接到触发器的“设置”端子的电阻器具有比另一个电阻器更低的电阻。
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5.发明授权公开(公告)号：US06498579B2
公开(公告)日：2002-12-24
申请号：US09838090
申请日：2001-04-18
申请人： Roberto Bardelli , Mario Tarantola
发明人： Roberto Bardelli , Mario Tarantola
IPC分类号： H03M134
摘要： A successive-approximation analog-digital converter including a logic control circuit timed by means of an external clock signal clock. The logic control circuit includes a register containing a first digital signal formed of N bits, which is the product of a first analog-digital conversion. The logic control circuit is suitable for producing a second digital signal formed of N bits through a second analog-digital conversion in N clock cycles. This analog-digital converter converts the second digital signal sent by the logic circuit to a second analog signal. A comparator compares the first analog signal with the second analog signal which has been input to the analog-digital converter. The converter includes a device which enables the increase of the first analog signal in output from the digital-analog converter and in input to the comparator by a preset value (Voffs) when the bit of the first digital signal which corresponds in position to the bit of the second digital signal which must be decided in a clock cycle is zero.
摘要翻译： 包括通过外部时钟信号时钟定时的逻辑控制电路的逐次逼近模数转换器。 逻辑控制电路包括寄存器，其包含由N位形成的第一数字信号，其是第一模数转换的乘积。 逻辑控制电路适用于通过N个时钟周期中的第二模拟数字转换产生由N位形成的第二数字信号。 该模拟数字转换器将由逻辑电路发送的第二数字信号转换为第二模拟信号。 比较器将第一模拟信号与已经输入到模拟数字转换器的第二模拟信号进行比较。 该转换器包括一个装置，当第一数字信号的位与位相对应时，该装置使得能够将来自数模转换器的输出中的第一模拟信号和输入到比较器中的预置值（Voffs）增加 必须在时钟周期内决定的第二数字信号为零。
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公开(公告)号：US6075391A
公开(公告)日：2000-06-13
申请号：US95735
申请日：1998-06-11
IPC分类号： H03K17/06 , H03K17/08 , H03K17/687
CPC分类号： H03K17/063 , H03K2217/0018
摘要： A circuit for charging a capacitance using an LDMOS integrated transistor functioning as a source follower and controlled, in a manner to emulate a high voltage charging diode of the capacitance. The LDMOS transistor is controlled via a bootstrap capacitor charged by a diode at the supply voltage of the circuit, and by an inverter driven by a logic control circuit as a function of a Low Gate Drive Signal and of a second logic signal which is active during a phase wherein the supply voltage is lower than the minimum switch-on voltage of the integrated circuit. The circuit uses a first zener diode to charge the bootstrap capacitor and the source of the transistor is connected to the supply node through a second zener diode.
摘要翻译： 用于使用用作源极跟随器的LDMOS集成晶体管对电容进行充电的电路，并且以模拟电容的高电压充电二极管的方式被控制。 LDMOS晶体管通过在电路的电源电压下由二极管充电的自举电容器和由作为低栅极驱动信号的函数的逻辑控制电路驱动的反相器以及在第二逻辑信号中被激活的第二逻辑信号来控制 其中电源电压低于集成电路的最小接通电压。 电路使用第一齐纳二极管对自举电容器充电，晶体管的源极通过第二齐纳二极管连接到电源节点。
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7.发明授权Protection circuit for controlling the gate voltage of a hv LDMOS transistor 失效用于控制hv LDMOS晶体管的栅极电压的保护电路
公开(公告)号：US6060948A
公开(公告)日：2000-05-09
申请号：US96272
申请日：1998-06-11
IPC分类号： H03K17/06 , H03K17/0812 , H03K17/16 , H03K7/162
CPC分类号： H03K17/08122 , H03K17/063
摘要： A circuit for charging a capacitance using an LDMOS integrated transistor functioning as a source follower stage and controlled, in a manner to emulate a high voltage charging diode of the capacitance via a bootstrap capacitor charged by a diode connected to the supply node of the circuit, and by an inverter driven by a logic control circuit as a function of a first Low Gate Drive Signal and of a second logic signal. The second logic signal is active during a phase where the supply voltage is lower than the minimum switch-on voltage of the integrated circuit. The circuit further includes a second inverter functionally referred to the charging node of the bootstrap capacitor and to the voltage of the output node of the inverter. The second inverter has an input coupled to the second logic signal and an output coupled to the gate node of the LDMOS transistor for preventing accidental undue switch-on of the LDMOS transistor.
摘要翻译： 一种用于使用用作源极跟随器级的LDMOS集成晶体管对电容进行充电的电路，并且以通过连接到电路的电源节点的二极管充电的自举电容来模拟电容的高电压充电二极管的方式进行控制， 以及由逻辑控制电路驱动的逆变器作为第一低栅极驱动信号和第二逻辑信号的函数。 第二逻辑信号在电源电压低于集成电路的最小接通电压的阶段有效。 电路还包括功能上称为自举电容器的充电节点的第二反相器和逆变器的输出节点的电压。 第二反相器具有耦合到第二逻辑信号的输入和耦合到LDMOS晶体管的栅极节点的输出，用于防止LDMOS晶体管的意外过度接通。
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公开(公告)号：US6031412A
公开(公告)日：2000-02-29
申请号：US96401
申请日：1998-06-11
CPC分类号： H03K17/063 , H03K2217/0018
摘要： A circuit for charging a capacitance using an LDMOS integrated transistor controlled in a manner to emulate a high voltage charging diode of the capacitance. The circuit avoids the switch-on of parasitic bipolar transistors of the LDMOS structure during transient states. The circuit includes a number of junctions directly biased between a source node and a body node of the LDMOS transistor, a current generator referred to a ground of the circuit, at least one switch between the source and a first junction of a chain of directly biased junctions, and a limiting resistor connected between the body and the current generator referred to ground. The switch is open during a charging phase of the capacitance and is closed when the charging voltage of the capacitance exceeds a preestablished threshold responsive to a control signal. The switch is controlled by a logic signal active during the phase in which the supply voltage of the integrated circuit is lower than the minimum switch-on voltage of the same integrated circuit, for charging the body with a current whose maximum value is limited to a preestablished value.
摘要翻译： 使用以模拟电容的高压充电二极管的方式控制的LDMOS集成晶体管对电容进行充电的电路。 该电路避免了在瞬态状态期间LDMOS结构的寄生双极晶体管的接通。 电路包括直接偏置在LDMOS晶体管的源极节点和体节点之间的多个结，称为电路接地的电流发生器，源极和直接偏置的链的第一结之间的至少一个开关 接头和连接在主体和电流发生器之间的限制电阻器是指地面。 开关在电容的充电阶段打开，并且当电容的充电电压响应于控制信号超过预先建立的阈值时闭合。 开关由在集成电路的电源电压低于同一集成电路的最小接通电压的相位中的逻辑信号控制，用于对电池充电，其电流的最大值被限制为 预先确定的价值。
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