摘要:
An integrated circuit has an input connection for connecting an external signal conductor that passes signals to execute functions in the device. The external signal conductor can pick up strong interfering signals with high frequency content, for example when the device is used in a car. To protect against unintended execution of functions the device contains a timer circuit comprising a capacitance and a current supplying circuit coupled to an integration node. A discharge diode is coupled between the input connection and the integration node, with a polarity such that the discharge diode, when in forward bias, is capable of draining current from the current supplying circuit. A detector is coupled to the integration node for generating a signal to be supplied to the integrated circuit device to respond to a signal transition on the conductor. The diode serves to reset integration on the integration node before the detector detects the transition in case of short pulses. By using a diode instead of a switching transistor the circuit is more robust against the effect of interfering pulses.
摘要:
Circuit arrangement, LIN comprising such circuit arrangement as well as method for processing input signals of the LIN In order to further develop a circuit arrangement (100)—for processing at least one input signal (12) from at least one data bus (10) of at least one LIN and—for providing the data bus (10) with at least one output signal (18), as well as a corresponding operating method in such way that EMI performance and/or EMI performance of the LIN (300) is improved, it is proposed to provide—at least one analog-digital converting circuit (ADC) for converting the analog input signal (12) into at least one digital signal (14) to be processed, and—at least one digital-analog converting circuit (DAC) for converting the processed digital signal (16) into the analog output signal (18).
摘要:
The sleep watchdog circuit for asynchronous circuits of the present invention contains clock means, counting means with multiple trigger input function and a digital supply. When the circuit is in the normal operation state, a periodic reset or activity signal is present that will reset the watchdog counter. As a result the clock means will keep on running, and the digital supply is operating in “normal” mode. When the circuit is put into the “sleep/standby” state, the “activity” signal becomes inactive, and if no wakeup events occur before the counter is finished the clock means will be put to a halt and the digital supply changes into a low power mode.
摘要:
An electronic circuit has a signal conductor (11), a power supply reference conductor (10) connected by a switching circuit. The switching circuit contains a PMOS transistor (17) and an NMOS transistor realized on a common substrate (100). The NMOS transistor (17) has a source coupled to the power supply reference conductor (10). The NMOS transistor (18) has a source coupled to the drain of the PMOS transistor (17), and a drain coupled to the signal conductor (11). A control circuit (13, 14, 15, 16) switches between an “on” state and an “off” state, in which the control circuit (13, 14, 15, 16) controls the gate source voltages of the first and second MOS transistor (17, 18) to make channels of these MOS transistors (17, 18) conductive and not to make the channels of these first and second transistors (17, 18) conductive respectively. Preferably a complementary switching circuit is also provided. The complementary switching circuit uses opposite polarity voltage differences, an NMOS transistor (27) coupled to a second power supply and a PMOS transistor (28) coupled to a signal conductor. The on resistances of the switching circuits are matched by matching the NMOS gate-source voltages, as well as the PMOS gate source voltages.