公开(公告)号：US4638187A

公开(公告)日：1987-01-20

申请号：US782639

申请日：1985-10-01

申请人： Clifford H. Boler ,  William W. Leake ,  Surinder S. Rai ,  Gene B. Zemske

发明人： Clifford H. Boler ,  William W. Leake ,  Surinder S. Rai ,  Gene B. Zemske

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0948 ,  H03K21/10

CPC分类号： H03K19/01721 ,  H03K19/0013 ,  H03K19/00361 ,  H03K19/018521 ,  H03K19/09429 ,  H03K19/0948

摘要： A CMOS output buffer provides high drive current without sacrificing speed and with minimum output signal distortion due to internal chip ground bounce or output signal ringing. The output buffer includes a pull-up circuit and a pull-down circuit which distribute switching current spikes over time. The pull-up circuit includes a P-channel FET and an N-channel FET connected in parallel between an output terminal and supply terminal V.sub.DD, with an inverter connected between the gates of the N-channel and P-channel FETs to provide the proper phase for the P-channel FET as well as delaying turn-on of the P-channel FET with respect to turn-on of the N-channel FET. The pull-down circuit includes a pair of N-channel FETs connected in parallel between the output terminal and ground, and a delay resistance connected between their gates so that turn-on of one of the N-channel FETs is delayed with respect to the other.

摘要翻译： CMOS输出缓冲器提供高驱动电流，而不会牺牲速度，并且由于内部芯片地面反弹或输出信号振铃，输出信号失真最小。 输出缓冲器包括上拉电路和下拉电路，其随时间分配开关电流尖峰。 上拉电路包括在输出端子和电源端子VDD之间并联连接的P沟道FET和N沟道FET，反相器连接在N沟道和P沟道FET的栅极之间，以提供适当的 P沟道FET的相位以及相对于N沟道FET的导通来延迟P沟道FET的导通。 下拉电路包括在输出端和地之间并联连接的一对N沟道FET，以及连接在其栅极之间的延迟电阻，使得N沟道FET之一的导通相对于 其他。