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1.发明授权Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical register 有权在体系结构寄存器中设置零位，用于存储较小尺寸的目标操作数，并基于附加到重命名的物理寄存器的相应零标志公开(公告)号：US08972701B2
公开(公告)日：2015-03-03
申请号：US13312131
申请日：2011-12-06
CPC分类号： G06F9/30003 , G06F1/3234 , G06F9/30014 , G06F9/30112 , G06F9/30189 , G06F9/384
摘要： A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilized for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.
摘要翻译： 提供了一种数据处理系统，其中要存储在体系结构寄存器内的目的地操作数被限制为具有作为前缀添加的零值，以便架构寄存器值具有固定的位宽度，而与目的地操作数的写入宽度无关。 而不是在数据路径中的任何地方添加这些零值，而是至少在用于寄存器重命名操作的物理寄存器和结果队列中将结果写入架构寄存器文件之前的零标志代表它们。 这节省了电路资源并降低了能耗。
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2.发明授权Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format 有权对不同的指令集映射相同的逻辑寄存器说明符，并使用通用地址格式与架构寄存器文件发散关联公开(公告)号：US08914615B2
公开(公告)日：2014-12-16
申请号：US13309732
申请日：2011-12-02
CPC分类号： G06F9/30145 , G06F9/30098 , G06F9/30112 , G06F9/3012 , G06F9/30174 , G06F9/34 , G06F9/3824 , G06F9/384
摘要： A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.
摘要翻译： 处理器核心支持从第一指令集和第二指令集两者执行程序指令。 包含架构寄存器的架构寄存器文件18由两个指令集共享。 两个指令集使用逻辑寄存器说明符，其中这些逻辑寄存器说明符的至少一些值对应于架构寄存器文件18内的不同结构寄存器。第一指令集的第一解码器4和用于第二指令集的第二解码器6 用于将逻辑寄存器说明符解码为公共寄存器寻址格式。 该公共寄存器寻址格式用于向重命名电路10提供寄存器说明符，用于结合物理寄存器文件16和架构寄存器文件18来支持寄存器重命名。
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公开(公告)号：US20120124340A1
公开(公告)日：2012-05-17
申请号：US12926374
申请日：2010-11-12
申请人： James Nolan Hardage
发明人： James Nolan Hardage
IPC分类号： G06F9/305
CPC分类号： G06F9/3836 , G06F9/30101 , G06F9/3834 , G06F9/3857
摘要： A processor 2 for performing out-of-order execution of a stream of program instructions includes a special register access pipeline for performing status access instructions accessing a status register 20. In order to serialise these status access instructions relative to other instructions within the system access timing control circuitry 32 permits dispatch of other instructions to proceed but controls the commit queue and the result queue such that no program instructions in program order succeeding the status access instruction are permitted to complete until after a trigger state has been detected in which all program instructions preceding in program order the status access instruction have been performed and made any updates to the architectural state. This is followed by the performance of the status access instruction itself.
摘要翻译： 用于执行程序指令流的无序执行的处理器2包括用于执行访问状态寄存器20的状态访问指令的专用寄存器访问流水线。为了将这些状态访问指令相对于系统访问内的其他指令进行串行化 定时控制电路32允许调度其他指令进行，但是控制提交队列和结果队列，使得在状态访问指令之后的程序顺序中的任何程序指令都不允许完成，直到检测到所有程序指令 在程序顺序之前，已经执行了状态访问指令，并对架构状态进行了任何更新。 之后是状态访问指令本身的执行。
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公开(公告)号：US20120124301A1
公开(公告)日：2012-05-17
申请号：US12926415
申请日：2010-11-16
IPC分类号： G06F12/00
CPC分类号： G06F9/3806 , G06F5/065 , G06F9/381
摘要： A loop buffer is provided with a main store 26 and an auxiliary store 28. The main store 26 stores micro-operation instructions. The auxiliary store 28 has fewer entries than the main store 26 and stores target addresses for predicted taken branch instructions stored within the main store 26. Read control circuitry serves to control reading from the main store and from an auxiliary store such that target addresses are read from the auxiliary store in association with the predicted taken branch instructions read from the main store.
摘要翻译： 环路缓冲器具有主存储器26和辅助存储器28.主存储器26存储微操作指令。 辅助存储器28具有比主存储器26少的条目，并且存储存储在主存储器26内的预测采集分支指令的目标地址。读控制电路用于控制从主存储器和辅助存储器的读取，从而读取目标地址 从辅助商店与从主店读取的预测的分支指令相关联。
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公开(公告)号：US20110016338A1
公开(公告)日：2011-01-20
申请号：US12458560
申请日：2009-07-15
CPC分类号： G06F9/30116 , G06F9/30087 , G06F9/3013 , G06F9/3861 , G06F9/3891
摘要： A processor is disclosed having a plurality of general purpose registers for storing data for processing by the processor; a set of system configuration registers for storing data indicative of a current configuration of the processor; the system configuration registers being located together in a register file; and at least some of the set of system configuration registers having a shadow register for storing a duplicate value remote from the register file, the shadow register being located close to a component that the shadow register stores a configuration value for.
摘要翻译： 公开了一种具有多个通用寄存器的处理器，用于存储由处理器处理的数据; 一组系统配置寄存器，用于存储指示处理器的当前配置的数据; 系统配置寄存器一起位于寄存器文件中; 并且所述一组系统配置寄存器中的至少一些具有用于存储远离寄存器文件的重复值的影子寄存器，所述影子寄存器位于靠近所述影子寄存器存储配置值的组件。
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公开(公告)号：US06408361B1
公开(公告)日：2002-06-18
申请号：US09389446
申请日：1999-09-02
IPC分类号： G06F1200
CPC分类号： G06F12/0846 , G06F12/0831 , G06F12/0864
摘要： The present invention provides a method and apparatus for allowing autonomous, way specific tag updates. More specifically, the invention provides way specific tag and status updates while concurrently allowing reads of the ways not currently being updated. If a read hit is determined, then the read is processed in a typical fashion. However, if the read is a read miss and one of the ways is flagged as being updated, then all ways are read again once the specific way has completed its updated.
摘要翻译： 本发明提供一种用于允许自主的，特定方式的标签更新的方法和装置。 更具体地，本发明提供方式特定的标签和状态更新，同时允许读取当前不被更新的方式。 如果确定了读命中，则以典型的方式处理读取。 但是，如果读取是未命中，并且其中一种方式被标记为更新，则一旦特定方式完成更新，就会再次读取所有方法。
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7.发明授权公开(公告)号：US06269360B1
公开(公告)日：2001-07-31
申请号：US09066012
申请日：1998-04-24
IPC分类号： G06F1730
CPC分类号： G06F13/161 , Y10S707/99932
摘要： Where a plurality of ordered transactions are received for data transfers on a pipelined bus, each transaction in the series is initiated before all prospective retry responses to the preceding ordered transactions may be asserted. The address responses to all preceding ordered transfers are then monitored in connection with performance of the newly initiated transfer. If a retry response to any preceding ordered transaction is asserted, a self-initiated retry response for all subsequent transactions, including the newly initiated transfer, is also asserted. The system-retried transactions and all succeeding, ordered transactions are immediately reattempted. The overlapping performance of the ordered transfers reduces the latency of non-retried transfers, achieving performance comparable to non-ordered transactions. Even where a retry response is asserted, the total latency required for completion of both transactions in the ordered pair is reduced by at least a portion of the address-to-response latency, so that the impact of ordering requirements on system performance is minimized. Strict ordering is thus enforced while taking full advantage of the pipelined nature of the bus to maximize utilization of the bus bandwidth.
摘要翻译： 在对流水线总线上的数据传输接收到多个有序事务的情况下，系列中的每个事务在所有对先前有序事务的预期重试响应可能被断言之前启动。 然后，与新发起的传输的性能相关联地监视对所有先前有序传输的地址响应。 如果对任何先前有序事务的重试响应被断言，则还会断言所有后续事务的自发起的重试响应，包括新发起的传输。 系统重试的交易和所有后续的有序交易立即被重新尝试。 有序传输的重叠性能降低了非重试传输的延迟，实现与非有序事务相当的性能。 即使在重试响应被断言的情况下，完成有序对中的两个事务所需的总延迟也减少了地址到响应延迟的至少一部分，从而将排序要求对系统性能的影响降到最低。 因此，在充分利用总线的流水线特性的同时强制执行严格排序，以最大限度地利用总线带宽。
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公开(公告)号：US20130145127A1
公开(公告)日：2013-06-06
申请号：US13312131
申请日：2011-12-06
CPC分类号： G06F9/30003 , G06F1/3234 , G06F9/30014 , G06F9/30112 , G06F9/30189 , G06F9/384
摘要： A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilised for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.
摘要翻译： 提供了一种数据处理系统，其中要存储在体系结构寄存器内的目的地操作数被限制为具有作为前缀添加的零值，以便架构寄存器值具有固定的位宽度，而与目的地操作数的写入宽度无关。 而不是在数据路径中的任何地方添加这些零值，而是至少在用于寄存器重命名操作的物理寄存器和结果队列中将结果写入架构寄存器文件之前的零标志代表它们。 这节省了电路资源并降低了能耗。
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公开(公告)号：US20130145126A1
公开(公告)日：2013-06-06
申请号：US13309732
申请日：2011-12-02
CPC分类号： G06F9/30145 , G06F9/30098 , G06F9/30112 , G06F9/3012 , G06F9/30174 , G06F9/34 , G06F9/3824 , G06F9/384
摘要： A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.
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10.发明授权Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism 有权重新命名宽的寄存器源操作数，具有多个短寄存器源操作数，用于使用现有机制快速检测依赖关系的选择指令公开(公告)号：US08386754B2
公开(公告)日：2013-02-26
申请号：US12457905
申请日：2009-06-24
申请人： Conrado Blasco Allue , David James Williamson , James Nolan Hardage , Glen Andrew Harris , Robert Gregory McDonald
发明人： Conrado Blasco Allue , David James Williamson , James Nolan Hardage , Glen Andrew Harris , Robert Gregory McDonald
IPC分类号： G06F9/38
CPC分类号： G06F9/30112 , G06F9/3017 , G06F9/3836 , G06F9/384
摘要： An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided. This slower mechanism may, for example, be to drain all the preceding micro-operations from the execution pipelines before issuing the micro-operation having the data hazard.
摘要翻译： 无序重命名处理器具有寄存器文件，在该寄存器文件中可能发生不同大小的寄存器之间的混叠。 以这种方式，具有双精度尺寸的源寄存器的程序指令可以使用两个单精度寄存器作为一个或多个先前程序指令的目的地。 为了跟踪这种数据依赖关系，双精度寄存器可以重新映射成指定两个单精度寄存器作为其源寄存器的微操作。 以这种方式，调度电路可以使用其现有的危险检测和管理机制来处理潜在的数据危害和依赖性。 并不是所有具有不同大小的寄存器之间的数据危害的程序指令都由该源寄存器重新映射来处理。 对于这些其他程序指令，提供了一种用于处理数据依赖性危害的较慢机制。 例如，这种较慢的机制可以在发出具有数据危险的微操作之前从执行管线中排出所有先前的微操作。
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