公开(公告)号：US09142557B2

公开(公告)日：2015-09-22

申请号：US14496797

申请日：2014-09-25

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Soogeun Lee

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L27/10844 ,  H01L21/76844 ,  H01L21/76865 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/75 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high capacitance embedded metal interconnect capacitor and associated fabrication processes are disclosed for using a directional barrier metal formation sequence in a dual damascene copper process to form multi-layer stacked copper interconnect structure having reduced barrier metal layer formation at the bottom of each via hole so that the multi-layer stacked copper interconnect structure may be readily removed and replaced with high capacitance MIM capacitor layers.

Abstract translation: 公开了一种高电容嵌入式金属互连电容器和相关的制造工艺，用于在双镶嵌铜工艺中使用方向性阻挡金属形成顺序，以形成在每个通孔底部形成减少的阻挡金属层的多层堆叠铜互连结构， 可以容易地去除多层堆叠铜互连结构并用高电容MIM电容器层代替。

公开(公告)号：US20150102461A1

公开(公告)日：2015-04-16

申请号：US14496797

申请日：2014-09-25

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Soogeun Lee

IPC: H01L27/108 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L27/10844 ,  H01L21/76844 ,  H01L21/76865 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/75 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high capacitance embedded metal interconnect capacitor and associated fabrication processes are disclosed for using a directional barrier metal formation sequence in a dual damascene copper process to form multi-layer stacked copper interconnect structure having reduced barrier metal layer formation at the bottom of each via hole so that the multi-layer stacked copper interconnect structure may be readily removed and replaced with high capacitance MIM capacitor layers.

Abstract translation: 公开了一种高电容嵌入式金属互连电容器和相关的制造工艺，用于在双镶嵌铜工艺中使用方向性阻挡金属形成顺序，以形成在每个通孔底部形成减少的阻挡金属层的多层堆叠铜互连结构， 可以容易地去除多层堆叠铜互连结构并用高电容MIM电容器层代替。

公开(公告)号：US20150021773A1

公开(公告)日：2015-01-22

申请号：US14312052

申请日：2014-06-23

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Soogeun Lee

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device and associated fabrication process are disclosed for forming a through semiconductor via (TSV) conductor structure in a semiconductor substrate with active circuitry formed on a first substrate surface where the TSV conductor structure includes multiple small diameter conductive vias extending through the first substrate surface and into the semiconductor substrate by a predetermined depth and a large diameter conductive via formed to extend from the multiple small diameter conductive vias and through a second substrate surface opposite to the first substrate surface.

Abstract translation: 公开了一种用于在半导体衬底中形成贯穿半导体通孔（TSV）导体结构的集成电路器件和相关的制造工艺，其中有源电路形成在第一衬底表面上，其中TSV导体结构包括延伸穿过第一衬底的多个小直径导电通孔 表面并通过形成为从多个小直径导电通孔延伸并通过与第一衬底表面相对的第二衬底表面的预定深度和大直径导电通孔进入半导体衬底。