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公开(公告)号：US20200220550A1
公开(公告)日：2020-07-09
申请号：US16240702
申请日：2019-01-04
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Arshan Aga , Xiang Gao , Ni Xu
Abstract: An illustrative PLL circuit and method for generating a clock signal over a wide frequency range without gaps. In one illustrative embodiment, an extended-range PLL includes: a phase comparator that determines a phase error between a reference clock and a feedback clock; a loop filter that converts the phase error into a control signal; a voltage controlled oscillator (VCO) that provides a generated clock signal having a generated clock frequency determined by the control signal; a divide-by-1.5 block that produces a reduced-frequency clock signal in response to the generated clock signal; and a multiplexer that selects one of the generated clock signal and the reduced-frequency clock signal as a selected clock signal.
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Patent Agency Ranking
公开(公告)号：US10778236B2
公开(公告)日：2020-09-15
申请号：US16240702
申请日：2019-01-04
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Arshan Aga , Xiang Gao , Ni Xu
Abstract: An illustrative PLL circuit and method for generating a clock signal over a wide frequency range without gaps. In one illustrative embodiment, an extended-range PLL includes: a phase comparator that determines a phase error between a reference clock and a feedback clock; a loop filter that converts the phase error into a control signal; a voltage controlled oscillator (VCO) that provides a generated clock signal having a generated clock frequency determined by the control signal; a divide-by-1.5 block that produces a reduced-frequency clock signal in response to the generated clock signal; and a multiplexer that selects one of the generated clock signal and the reduced-frequency clock signal as a selected clock signal.
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公开(公告)号：US10727786B2
公开(公告)日：2020-07-28
申请号：US16653701
申请日：2019-10-15
Applicant: Credo Technology Group Limited
Inventor： Xiang Gao
Abstract: Integrated circuits such as multi-channel transceivers may share oscillators having loop inductors. To minimize the driving distance from the shared oscillators to the transceiver modules, the loop inductor may be equipped with an additional sense port diametrically opposite to the drive port. An oscillator drive core may be coupled to the drive port to provide an oscillating signal at the drive and sense ports. The oscillating signals can be converted into digital clock signals by way of a differential amplifier. Three-loop inductor designs and/or multi-winding inductor designs may be preferred for minimizing parasitic effects of the added sense port.
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公开(公告)号：US20180219513A1
公开(公告)日：2018-08-02
申请号：US15423398
申请日：2017-02-02
Applicant: Credo Technology Group Limited
Inventor： Xiang Gao
CPC classification number: H03B5/1215 , H01F5/003 , H01F17/0006 , H01F2005/043 , H01L28/10 , H03B5/1228
Abstract: Integrated circuits such as multi-channel transceivers may share oscillators having loop inductors. To minimize the driving distance from the shared oscillators to the transceiver modules, the loop inductor may be equipped with an additional sense port diametrically opposite to the drive port. An oscillator drive core may be coupled to the drive port to provide an oscillating signal at the drive and sense ports. The oscillating signals can be converted into digital clock signals by way of a differential amplifier. Three-loop inductor designs and/or multi-winding inductor designs may be preferred for minimizing parasitic effects of the added sense port.
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公开(公告)号：US20200044604A1
公开(公告)日：2020-02-06
申请号：US16653701
申请日：2019-10-15
Applicant: Credo Technology Group Limited
Inventor： Xiang Gao
Abstract: Integrated circuits such as multi-channel transceivers may share oscillators having loop inductors. To minimize the driving distance from the shared oscillators to the transceiver modules, the loop inductor may be equipped with an additional sense port diametrically opposite to the drive port. An oscillator drive core may be coupled to the drive port to provide an oscillating signal at the drive and sense ports. The oscillating signals can be converted into digital clock signals by way of a differential amplifier. Three-loop inductor designs and/or multi-winding inductor designs may be preferred for minimizing parasitic effects of the added sense port.
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公开(公告)号：US10483910B2
公开(公告)日：2019-11-19
申请号：US15423398
申请日：2017-02-02
Applicant: Credo Technology Group Limited
Inventor： Xiang Gao
Abstract: Integrated circuits such as multi-channel transceivers may share oscillators having loop inductors. To minimize the driving distance from the shared oscillators to the transceiver modules, the loop inductor may be equipped with an additional sense port diametrically opposite to the drive port. An oscillator drive core may be coupled to the drive port to provide an oscillating signal at the drive and sense ports. The oscillating signals can be converted into digital clock signals by way of a differential amplifier. Three-loop inductor designs and/or multi-winding inductor designs may be preferred for minimizing parasitic effects of the added sense port.
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