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1.发明授权Floating point round-off amount determination processors, methods, systems, and instructions 有权浮点数四舍五入确定处理器，方法，系统和说明公开(公告)号：US09513871B2
公开(公告)日：2016-12-06
申请号：US13977257
申请日：2011-12-30
CPC分类号： G06F9/3001 , G06F7/483 , G06F7/49947 , G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/3013
摘要： A method of an aspect includes receiving a floating point round-off amount determination instruction. The instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point, and indicates a destination storage location. A result including one or more result floating point data elements is stored in the destination storage location in response to the floating point round-off amount determination instruction. Each of the one or more result floating point data elements includes a difference between a corresponding floating point data element of the source in a corresponding position, and a rounded version of the corresponding floating point data element of the source that has been rounded to the indicated number of the fraction bits. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一种方面的方法包括接收浮点舍入量确定指令。 该指令指示一个或多个浮点数据元素的源，指示小数点之后的小数位数，并指示目的地存储位置。 包括一个或多个结果浮点数据元素的结果响应于浮点舍入量确定指令被存储在目的地存储位置中。 一个或多个结果浮点数据元素中的每一个包括相应位置的源的相应浮点数据元素与已被舍入到指示的源的相应浮点数据元素的舍入版本之间的差 小数位数。 公开了其它方法，装置，系统和指令。
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公开(公告)号：US20130290685A1
公开(公告)日：2013-10-31
申请号：US13976792
申请日：2011-12-22
申请人： Jesus Corbal San Adrian , Cristina S. Anderson , Robert Valentine , Bret Toll , Amit Gradstein , Simon Rubanovich , Benny Eitan
发明人： Jesus Corbal San Adrian , Cristina S. Anderson , Robert Valentine , Bret Toll , Amit Gradstein , Simon Rubanovich , Benny Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30036
摘要： A method of an aspect includes receiving a floating point rounding instruction. The floating point rounding instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point that each of the one or more floating point data elements are to be rounded to, and indicates a destination storage location. A result is stored in the destination storage location in response to the floating point rounding instruction. The result includes one or more rounded result floating point data elements. Each of the one or more rounded result floating point data elements includes one of the floating point data elements of the source, in a corresponding position, which has been rounded to the indicated number of fraction bits. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一方面的方法包括接收浮点舍入指令。 浮点舍入指令指示一个或多个浮点数据元素的源，指示在一个或多个浮点数据元素中的每一个要四舍五入的基数点之后的分数比特的数量，并且指示目的地存储位置 。 响应于浮点舍入指令，结果存储在目的地存储位置。 结果包括一个或多个舍入结果浮点数据元素。 一个或多个圆化结果浮点数据元素中的每一个包括源的浮点数据元素中的一个，在对应位置中，其被舍入到所指示的小数位数。 公开了其它方法，装置，系统和指令。
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公开(公告)号：US10209986B2
公开(公告)日：2019-02-19
申请号：US13976792
申请日：2011-12-22
申请人： Jesus Corbal San Adrian , Cristina S. Anderson , Robert Valentine , Bret Toll , Amit Gradstein , Simon Rubanovich , Benny Eitan
发明人： Jesus Corbal San Adrian , Cristina S. Anderson , Robert Valentine , Bret Toll , Amit Gradstein , Simon Rubanovich , Benny Eitan
IPC分类号： G06F9/30
摘要： A method of an aspect includes receiving a floating point rounding instruction. The floating point rounding instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point that each of the one or more floating point data elements are to be rounded to, and indicates a destination storage location. A result is stored in the destination storage location in response to the floating point rounding instruction. The result includes one or more rounded result floating point data elements. Each of the one or more rounded result floating point data elements includes one of the floating point data elements of the source, in a corresponding position, which has been rounded to the indicated number of fraction bits. Other methods, apparatus, systems, and instructions are disclosed.
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公开(公告)号：US08706789B2
公开(公告)日：2014-04-22
申请号：US12976359
申请日：2010-12-22
IPC分类号： G06F7/38
CPC分类号： G06F7/535 , G06F7/5525 , G06F9/30014 , G06F2207/5356 , G06F2207/5521
摘要： In one embodiment, the present invention includes a method for receiving a reciprocal instruction and an operand in a processor, accessing an entry of a lookup table based on a portion of the operand and the instruction, generating an encoder output based on a type of the reciprocal instruction and whether the reciprocal instruction is a legacy instruction, and selecting portions of the lookup table entry and input operand to be provided to a reciprocal logic unit based on the encoder output. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于在处理器中接收互逆指令和操作数的方法，其基于所述操作数和所述指令的一部分访问查找表的条目，基于所述操作数的类型生成编码器输出 互逆指令以及互易指令是否是遗留指令，以及基于编码器输出来选择要提供给倒数逻辑单元的查找表项和输入操作数的部分。 描述和要求保护其他实施例。
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5.发明申请MULTIPLY ADD FUNCTIONAL UNIT CAPABLE OF EXECUTING SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE AND CLASS INSTRUCTIONS 有权多功能功能单元，可执行规模，圆形，GETEXP，圆形，确定，减少，范围和类别说明公开(公告)号：US20120079251A1
公开(公告)日：2012-03-29
申请号：US12890543
申请日：2010-09-24
CPC分类号： G06F7/57 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/49947 , G06F7/49957 , G06F7/5443 , G06F9/30014 , G06F9/3893
摘要： A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction.
摘要翻译： 描述了涉及用功能单元执行第一指令的方法。 第一条指令是乘法加法指令。 该方法还包括执行与功能单元的第二指令。 第二个指令是一个圆形指令。
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6.发明授权Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions 有权增加功能单元，能够执行刻度，圆形，GETEXP，圆形，GETMANT，缩小，范围和类指令公开(公告)号：US08914430B2
公开(公告)日：2014-12-16
申请号：US12890543
申请日：2010-09-24
CPC分类号： G06F7/57 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/49947 , G06F7/49957 , G06F7/5443 , G06F9/30014 , G06F9/3893
摘要： A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction.
摘要翻译： 描述了涉及用功能单元执行第一指令的方法。 第一条指令是乘法加法指令。 该方法还包括执行与功能单元的第二指令。 第二个指令是一个圆形指令。
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公开(公告)号：US20120166509A1
公开(公告)日：2012-06-28
申请号：US12976359
申请日：2010-12-22
IPC分类号： G06F7/38
CPC分类号： G06F7/535 , G06F7/5525 , G06F9/30014 , G06F2207/5356 , G06F2207/5521
摘要： In one embodiment, the present invention includes a method for receiving a reciprocal instruction and an operand in a processor, accessing an entry of a lookup table based on a portion of the operand and the instruction, generating an encoder output based on a type of the reciprocal instruction and whether the reciprocal instruction is a legacy instruction, and selecting portions of the lookup table entry and input operand to be provided to a reciprocal logic unit based on the encoder output. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于在处理器中接收互逆指令和操作数的方法，其基于所述操作数和所述指令的一部分访问查找表的条目，基于所述操作数的类型生成编码器输出 互逆指令以及互易指令是否是遗留指令，以及基于编码器输出来选择要提供给倒数逻辑单元的查找表项和输入操作数的部分。 描述和要求保护其他实施例。
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公开(公告)号：US09658850B2
公开(公告)日：2017-05-23
申请号：US13976993
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30029 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.
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公开(公告)号：US09619236B2
公开(公告)日：2017-04-11
申请号：US13976992
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3013 , G06F9/30167 , G06F9/3802
摘要： An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.
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10.发明申请APPARATUS AND METHOD FOR BROADCASTING FROM A GENERAL PURPOSE REGISTER TO A VECTOR REGISTER 审中-公开从通用寄存器向矢量寄存器广播的装置和方法公开(公告)号：US20140059322A1
公开(公告)日：2014-02-27
申请号：US13996800
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L Toll , Mark J Charney , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L Toll , Mark J Charney , Zeev Sperber , Amit Gradstein
IPC分类号： G06F15/80
摘要： An apparatus and method are described for broadcasting from a general purpose source register to a destination vector register. For example, a method according to one embodiment includes the following operations: selecting data element position N within the destination vector register to be updated; broadcasting a set of data from the general purpose source register to data element position N within the destination vector register if a mask indicator is set to a first indication; and either copying zeroes to data element position N within the destination vector register or maintaining existing values stored within data element position N within the destination vector register if the mask indicator is set to a second indication.
摘要翻译： 描述了用于从通用源寄存器到目的地向量寄存器的广播的装置和方法。 例如，根据一个实施例的方法包括以下操作：选择要更新的目的地向量寄存器内的数据元素位置N; 如果将掩码指示符设置为第一指示，则将一组数据从通用源寄存器传送到目的地向量寄存器内的数据元素位置N; 并且如果掩模指示符被设置为第二指示，则将零值复制到目的地向量寄存器内的数据元素位置N，或者保持存储在目的地向量寄存器内的数据元素位置N内的现有值。
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