公开(公告)号：US10699785B2

公开(公告)日：2020-06-30

申请号：US16144771

申请日：2018-09-27

申请人： Crossbar, Inc.

发明人： Mehdi Asnaashari ,  Hagop Nazarian ,  Christophe Sucur ,  Sylvain Dubois

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C7/18 ,  G11C8/12 ,  G11C29/42 ,  G11C29/44 ,  G11C8/14 ,  G06F17/16 ,  G11C29/04

摘要： Provided herein is a computing memory architecture. The non-volatile memory architecture can comprise a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines, a first data interface for receiving data from an external device and for outputting data to the external device, and a second data interface for outputting data to the external device. The non-volatile memory architecture can also comprise programmable processing elements connected to respective sets of the multiple sets of bitlines of the resistive random access memory array, and connected to the data interface. The programmable processing elements are configured to receive stored data from the resistive random access memory array via the respective sets of bitlines or to receive external data from the external device via the data interface, and execute a logical or mathematical algorithm on the external data or the stored data and generate processed data.

公开(公告)号：US11222696B1

公开(公告)日：2022-01-11

申请号：US16917261

申请日：2020-06-30

申请人： Crossbar, Inc.

发明人： Mehdi Asnaashari ,  Hagop Nazarian ,  Christophe Sucur ,  Sylvain Dubois

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C8/12 ,  G11C29/42 ,  G11C29/44 ,  G11C8/14 ,  G06F17/16 ,  G11C7/18 ,  G11C29/04

摘要： Provided herein is a computing memory architecture. The non-volatile memory architecture can comprise a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines, a first data interface for receiving data from an external device and for outputting data to the external device, and a second data interface for outputting data to the external device. The non-volatile memory architecture can also comprise programmable processing elements connected to respective sets of the multiple sets of bitlines of the resistive random access memory array, and connected to the data interface. The programmable processing elements are configured to receive stored data from the resistive random access memory array via the respective sets of bitlines or to receive external data from the external device via the data interface, and execute a logical or mathematical algorithm on the external data or the stored data and generate processed data.

公开(公告)号：US11127460B2

公开(公告)日：2021-09-21

申请号：US16144765

申请日：2018-09-27

申请人： Crossbar, Inc.

发明人： Mehdi Asnaashari ,  Hagop Nazarian ,  Christophe Sucur ,  Sylvain Dubois

IPC分类号： G11C13/00 ,  G11C7/18 ,  G11C8/12 ,  G11C29/42 ,  G11C29/44 ,  G11C8/14 ,  G06F17/16 ,  G11C29/04

摘要： Provided herein resistive random access memory matrix multiplication structures and methods. A non-volatile memory logic system can comprise a bit line and at a set of wordlines. Also included can be a set of resistive switching memory cells at respective intersections between the bit line and the set of wordlines. The set of resistive switching memory cells are programmed with a value of an input data bit of a first data matrix and receive respective currents on the set of wordlines. The respective currents comprise respective values of an activation data bit of a second data matrix. A resulting value based on a matrix multiplication corresponds to an output value of the bit line.

公开(公告)号：US20190103162A1

公开(公告)日：2019-04-04

申请号：US16144771

申请日：2018-09-27

申请人： Crossbar, Inc.

发明人： Mehdi Asnaashari ,  Hagop Nazarian ,  Christophe Sucur ,  Sylvain Dubois

IPC分类号： G11C13/00 ,  G11C7/18 ,  G11C8/14 ,  G11C8/12 ,  G11C29/42 ,  G11C29/44

摘要： Provided herein is a computing memory architecture. The non-volatile memory architecture can comprise a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines, a first data interface for receiving data from an external device and for outputting data to the external device, and a second data interface for outputting data to the external device. The non-volatile memory architecture can also comprise programmable processing elements connected to respective sets of the multiple sets of bitlines of the resistive random access memory array, and connected to the data interface. The programmable processing elements are configured to receive stored data from the resistive random access memory array via the respective sets of bitlines or to receive external data from the external device via the data interface, and execute a logical or mathematical algorithm on the external data or the stored data and generate processed data.

公开(公告)号：US20190102358A1

公开(公告)日：2019-04-04

申请号：US16144765

申请日：2018-09-27

申请人： Crossbar, Inc.

发明人： Mehdi Asnaashari ,  Hagop Nazarian ,  Christophe Sucur ,  Sylvain Dubois

IPC分类号： G06F17/16 ,  G11C13/00

摘要： Provided herein resistive random access memory matrix multiplication structures and methods. A non-volatile memory logic system can comprise a bit line and at a set of wordlines. Also included can be a set of resistive switching memory cells at respective intersections between the bit line and the set of wordlines. The set of resistive switching memory cells are programmed with a value of an input data bit of a first data matrix and receive respective currents on the set of wordlines. The respective currents comprise respective values of an activation data bit of a second data matrix. A resulting value based on a matrix multiplication corresponds to an output value of the bit line.