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    DIFFERENTIAL PROGRAMMING OF TWO-TERMINAL MEMORY WITH INTRINSIC ERROR SUPPRESSION AND WORDLINE COUPLING
    1.
    发明公开
    DIFFERENTIAL PROGRAMMING OF TWO-TERMINAL MEMORY WITH INTRINSIC ERROR SUPPRESSION AND WORDLINE COUPLING 审中-公开

    公开(公告)号：US20240071490A1

    公开(公告)日：2024-02-29

    申请号：US17895129

    申请日：2022-08-25

    申请人： Crossbar, Inc.

    发明人： Hagop Nazarian

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0059 ,  G11C13/004 ,  G11C13/0069

    摘要： Improved differential programming of multiple two-terminal memory cells that define an identifier bit is provided. A differential circuit can be defined by a plurality of resistive memory cells connected to a single bitline of an array, with respective wordlines coupling second terminals of the memory cells to ground (or low voltage). Some disclosed circuits can provide very rapid intrinsic suppression of a non-programmed memory cell(s) defining an identifier bit in response to programming of another memory cell (or group of cells) defining the identifier bit. Disclosed differential programming can reduce power consumption and mitigate or avoid invalid data results for an identifier bit.

    State change detection for two-terminal memory
    2.
    发明授权
    State change detection for two-terminal memory 有权

    公开(公告)号：US10796751B1

    公开(公告)日：2020-10-06

    申请号：US16261696

    申请日：2019-01-30

    申请人： Crossbar, Inc.

    发明人： Sang Nguyen ,  Hagop Nazarian ,  Tianhong Yan

    IPC分类号： G11C11/419 ,  G11C8/18 ,  G11C7/10 ,  G11C11/418 ,  G11C7/06 ,  G11C13/00

    摘要： A detection circuit that can detect a two-terminal memory cell changing state. For example, in response to electrical stimuli, a memory cell will change state, e.g., to a defined higher resistance state or a defined lower resistance state. Other, techniques do not detect this state change until after the stimuli is completed and a subsequent sensing operation (e.g., read pulse) is performed. The detection circuit can detect the state change during application of the electrical stimuli that cause the state change and can do so by comparing the magnitudes or values of two particular current parameters.

    NETWORK ROUTER DEVICE WITH HARDWARE-IMPLEMENTED LOOKUPS INCLUDING TWO-TERMINAL NON-VOLATILE MEMORY
    3.
    发明申请
    NETWORK ROUTER DEVICE WITH HARDWARE-IMPLEMENTED LOOKUPS INCLUDING TWO-TERMINAL NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20190259452A1

    公开(公告)日：2019-08-22

    申请号：US16398943

    申请日：2019-04-30

    申请人： Crossbar, Inc.

    发明人： Mehdi Asnaashari ,  Hagop Nazarian

    IPC分类号： G11C13/00 ,  G11C11/16 ,  G11C15/04 ,  G06F12/02 ,  G11C15/02

    摘要： A non-volatile programmable circuit configurable to perform logic functions, is provided. The programmable circuit can employ two-terminal non-volatile memory devices to store information, thereby mitigating or avoiding disturbance of programmed data in the absence of external power. Two-terminal resistive switching memory devices having high current on/off ratios and fast switching times can also be employed for high performance, and facilitating a high density array. For look-up table applications, input/output response times can be several nanoseconds or less, facilitating much faster response times than a memory array access for retrieving stored data.

    Non-volatile resistive memory configuration cell for field programmable gate array
    4.
    发明授权
    Non-volatile resistive memory configuration cell for field programmable gate array 有权

    公开(公告)号：US10199105B2

    公开(公告)日：2019-02-05

    申请号：US15592999

    申请日：2017-05-11

    申请人： Crossbar, Inc.

    发明人： Lin Shih Liu ,  Hagop Nazarian

    IPC分类号： G11C5/06 ,  G11C14/00 ,  G11C11/419 ,  G11C13/00 ,  G11C11/412

    摘要： Providing for a configuration cells for junction nodes of a field programmable gate array (FPGA) is described herein. By way of example, a configuration cell can comprise non-volatile resistive switching memory to facilitate programmable storage of data as an input to a control circuit of a junction node. The control circuit can activate or deactivate a junction node of the FPGA in response to a value of the data stored in the non-volatile resistive switching memory. The control circuit can comprise an SRAM circuit for fast operation of the junction node. Moreover, the non-volatile memory of the configuration cell facilitates fast power-up of the control circuit utilizing data stored in the resistive switching memory, and minimizes power consumption associated with storing the data.

    Multi-buffered shift register input matrix to FPGA
    6.
    发明授权
    Multi-buffered shift register input matrix to FPGA 有权

    公开(公告)号：US10050629B1

    公开(公告)日：2018-08-14

    申请号：US15610829

    申请日：2017-06-01

    申请人： Crossbar, Inc.

    发明人： Mehdi Asnaashari ,  Hagop Nazarian

    IPC分类号： H03K19/17 ,  G11C19/38 ,  H03K19/177 ,  H03K19/00

    摘要： A method for an FPGA includes programming a RRAM memory array with a first bit pattern, shifting the first bit pattern to a shift register array, employing the first bit pattern in operation of the FPGA, programming a RRAM memory array with a second bit pattern concurrent the employing the bit pattern in operation of the FPGA, shifting the second bit pattern to the shift register array, and employing the second bit pattern in operation of the FPGA.