Method and apparatus for dynamic plasma treatment of bipolar ESC system
    1.
    发明授权
    Method and apparatus for dynamic plasma treatment of bipolar ESC system 有权
    双相ESC系统动态等离子体处理方法及装置

    公开(公告)号:US07511936B2

    公开(公告)日:2009-03-31

    申请号:US11425006

    申请日:2006-06-19

    IPC分类号: H02N13/00

    CPC分类号: H01L21/67069

    摘要: The disclosure generally relates to a method for method for plasma etching a substrate in a plasma reactor comprising positioning the substrate on an electrostatic chuck inside the plasma reactor; supplying a DC voltage to the chuck, the DC voltage forming an electrostatic charge buildup on the substrate; plasma etching the substrate; disconnecting the DC voltage to the chuck; and counteracting the electrostatic charge buildup on the substrate by discharging a varying RF signal within the chamber.

    摘要翻译: 本发明一般涉及用于等离子体蚀刻等离子体反应器中的衬底的方法的方法,包括将衬底定位在等离子体反应器内的静电吸盘上; 向所述卡盘供应DC电压,所述DC电压在所述基板上形成静电电荷; 等离子体蚀刻基板; 断开直流电压到卡盘; 并通过在室内排放变化的RF信号来抵消衬底上的静电电荷积累。

    Method for forming a delamination resistant multi-layer dielectric layer for passivating a conductor layer
    2.
    发明授权
    Method for forming a delamination resistant multi-layer dielectric layer for passivating a conductor layer 有权
    用于形成用于钝化导体层的耐分层涂层的多层电介质层的方法

    公开(公告)号:US06245666B1

    公开(公告)日:2001-06-12

    申请号:US09541483

    申请日:2000-04-03

    IPC分类号: H01L21302

    摘要: Within a method for forming a microelectronic fabrication, there is first provided a substrate. There is then formed over the substrate a blanket aluminum containing conductor layer. There is then formed over the blanket aluminum containing conductor layer a masking layer. There is then etched, while employing a plasma etch method, the blanket aluminum containing conductor layer to form a patterned aluminum containing conductor layer while employing the masking layer as an etch mask layer, where the plasma etch method employs an etchant gas composition comprising at least one fluorine containing etchant gas and at least one halogen containing etchant gas other than a fluorine containing etchant gas. There is then formed contacting the patterned aluminum containing conductor layer a conformal dielectric liner layer. There is then formed upon the conformal dielectric liner layer a spin-on-glass (SOG) planarizing layer. Finally, there is then thermally annealed the spin-on-glass (SOG) planarizing layer to form a thermally cured spin-on-glass (SOG) planarizing layer. By employing the at least one fluorine containing etchant gas in conjunction with the at least one halogen containing etchant gas other than the fluorine containing etchant gas within the etchant gas composition for forming from the blanket aluminum containing conductor layer the patterned aluminum containing conductor layer, there is attenuated a delamination of the thermally cured spin-on-glass (SOG) planarizing layer from the conformal dielectric liner layer.

    摘要翻译: 在用于形成微电子制造的方法中,首先提供衬底。 然后在衬底上形成覆盖有铝的导体层。 然后在覆盖有铝的导体层上形成掩蔽层。 然后在使用等离子体蚀刻方法的同时使用等离子体蚀刻方法蚀刻含有铝的包覆导体层,以形成图案化的含铝导体层,同时使用掩模层作为蚀刻掩模层,其中等离子体蚀刻方法采用至少包括蚀刻剂气体组成 一种含氟蚀刻剂气体和除含氟蚀刻剂气体之外的至少一种含卤素的蚀刻剂气体。 然后形成与图案化的含铝导体层接触共形电介质衬垫层。 然后在保形绝缘衬垫层上形成旋涂玻璃(SOG)平坦化层。 最后,然后对旋涂玻璃(SOG)平坦化层进行热退火以形成热固化的旋涂玻璃(SOG)平坦化层。 通过使用至少一种含氟蚀刻剂气体与除腐蚀剂气体组合物中除含氟蚀刻剂气体之外的至少一种含卤素蚀刻剂气体一起,从含铝的导体层形成图案化的含铝导体层,那里 减弱了热固化的旋涂玻璃(SOG)平坦化层从共形绝缘衬垫层的分层。

    Method for edge profile and design rules control
    3.
    发明授权
    Method for edge profile and design rules control 失效
    边缘轮廓和设计规则控制方法

    公开(公告)号:US5877092A

    公开(公告)日:1999-03-02

    申请号:US877985

    申请日:1997-06-18

    CPC分类号: H01L21/31105 H01L21/76804

    摘要: A method is described which uses the differential etch behaviour of two different kinds of sequentially deposited silicon oxide layers in conjunction with controlled thicknesses and etching conditions to allow the etching of features such as via contact holes, oxide sidewalls, and crossover insulation edges to produce non-abrupt step height profiles for better edge coverage while still maintaining close adherence to minimum spacing design ground rules between adjacent features.

    摘要翻译: 描述了一种方法,其使用两种不同种类的顺序沉积的氧化硅层的差分蚀刻行为以及受控的厚度和蚀刻条件,以允许蚀刻诸如通孔接触孔,氧化物侧壁和交叉绝缘边缘之类的特征, - 突破阶梯高度轮廓,以实现更好的边缘覆盖,同时仍然保持紧密附着在相邻特征之间的最小间距设计基准规则。

    Method for forming DRAM stacked capacitor
    4.
    发明授权
    Method for forming DRAM stacked capacitor 失效
    形成DRAM叠层电容器的方法

    公开(公告)号:US5943582A

    公开(公告)日:1999-08-24

    申请号:US851115

    申请日:1997-05-05

    IPC分类号: H01L21/02 H01L21/20

    CPC分类号: H01L28/87 H01L28/91

    摘要: The present invention discloses a method for forming DRAM stacked capacitors by utilizing a densified oxide layer as an etch-stop for the wet etching process of an upper oxide layer in forming a contact hole for the stacked capacitor and thus, eliminating the need of a silicon nitride etch-stop layer and the occurrence of numerous processing difficulties normally observed in such stacked capacitor forming process. The lower oxide layer can be formed by a BPTEOS chemistry while the upper oxide layer can be formed by an ozone-TEOS chemistry.

    摘要翻译: 本发明公开了一种用于形成DRAM堆叠电容器的方法,该方法通过利用致密氧化物层作为用于形成层叠电容器的接触孔的上氧化层的湿式蚀刻工艺的蚀刻停止层,从而不需要硅 氮化物蚀刻停止层和在这种堆叠电容器形成过程中通常观察到的许多处理困难的发生。 低氧化物层可以通过BPTEOS化学形成,而上部氧化物层可以通过臭氧-TEOS化学形成。

    Plasma etch method for forming residue free fluorine containing plasma
etched layers
    5.
    发明授权
    Plasma etch method for forming residue free fluorine containing plasma etched layers 失效
    用于形成无残余氟等离子体蚀刻层的等离子体蚀刻方法

    公开(公告)号:US5872061A

    公开(公告)日:1999-02-16

    申请号:US958429

    申请日:1997-10-27

    IPC分类号: H01L21/311 H01L21/302

    CPC分类号: H01L21/02063 H01L21/31116

    摘要: A method for forming a patterned fluorine containing plasma etched layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a fluorine containing plasma etchable layer. There is then formed upon the fluorine containing plasma etchable layer a patterned photoresist layer. There is then etched through a fluorine containing plasma etching method while employing the patterned photoresist layer as a photoresist etch mask layer the fluorine containing plasma etchable layer to form a patterned fluorine containing plasma etched layer. The patterned fluorine containing plasma etched layer has a fluoropolymer residue layer formed thereupon. The fluorine containing plasma etch method employs a first etchant gas composition comprising a nitrogen trifluoride etchant gas. Finally, there is stripped through an oxygen containing plasma stripping method the patterned photoresist layer and the fluoropolymer residue layer from the patterned fluorine containing plasma etched layer. The oxygen containing plasma stripping method employs a second etchant gas composition comprising a fluorine containing etchant gas and an oxygen containing etchant gas.

    摘要翻译: 一种用于在微电子学制造中形成图案化含氟等离子体蚀刻层的方法。 首先提供了在微电子制造中使用的衬底。 然后在衬底上形成含氟等离子体可蚀刻层。 然后在含氟等离子体可蚀刻层上形成图案化的光致抗蚀剂层。 然后通过含氟等离子体蚀刻方法蚀刻,同时使用图案化的光致抗蚀剂层作为含氟等离子体可蚀刻层的光致抗蚀剂蚀刻掩模层,以形成图案化含氟等离子体蚀刻层。 图案化的含氟等离子体蚀刻层在其上形成有氟聚合物残留层。 含氟等离子体蚀刻方法使用包含三氟化氮蚀刻剂气体的第一蚀刻剂气体组合物。 最后,通过含氧等离子体剥离方法从图案化的含氟等离子体蚀刻层剥离图案化的光致抗蚀剂层和含氟聚合物残余物层。 含氧等离子体汽提方法采用包含含氟蚀刻剂气体和含氧蚀刻剂气体的第二蚀刻剂气体组合物。

    Method to prevent oxide peeling induced by sog etchback on the wafer edge
    6.
    发明授权
    Method to prevent oxide peeling induced by sog etchback on the wafer edge 失效
    防止晶片边缘上的回蚀引起的氧化物剥离的方法

    公开(公告)号:US5783482A

    公开(公告)日:1998-07-21

    申请号:US928228

    申请日:1997-09-12

    摘要: A method for avoiding oxide peeling by removing polymer contaminants from the edge of a wafer is described. An interlevel dielectric sandwich layer is formed by depositing a first oxide layer overlying semiconductor device structures in and on a semiconductor substrate, coating a spin-on-glass layer overlying the first oxide layer and rinsing the spin-on-glass layer whereby an edge bead rinse hump is formed a first distance from the edge of the wafer, etching back the spin-on-glass layer wherein the wafer is held by a clamp a second distance from the edge of the wafer wherein the second distance is smaller than the first distance and wherein the etching back of the spin-on-glass layer forms the polymer on the surface of the first oxide layer under the clamp at a third distance between the first and second distances, and depositing a second oxide layer overlying the etched back spin-on-glass layer and the polymer at the edge of the wafer to complete the interlevel dielectric sandwich layer. A layer of photoresist is coated overlying the sandwich layer wherein the photoresist layer does not extend closer to the edge of the wafer than the third distance and patterned to form a photoresist mask. The interlevel dielectric sandwich layer is etched away where it is not covered by the mask to form via openings wherein the second oxide layer overlying the polymer is etched away. The photoresist mask is stripped whereby the polymer is also removed thereby avoiding oxide peeling at the edge of the wafer.

    摘要翻译: 描述了通过从晶片的边缘去除聚合物污染物来避免氧化物剥离的方法。 通过在半导体衬底上和半导体衬底上沉积半导体器件结构上的第一氧化物层,涂覆覆盖第一氧化物层的旋涂玻璃层并漂洗旋涂玻璃层,从而形成边缘焊料 冲洗隆起形成与晶片边缘的第一距离,蚀刻回旋涂玻璃层,其中晶片由夹具保持第二距离离晶片边缘的距离,其中第二距离小于第一距离 并且其中所述旋涂玻璃层的所述蚀刻反应在所述夹具下方的所述第一氧化物层的表面上在所述第一和第二距离之间的第三距离处形成所述聚合物,并且沉积覆盖所述蚀刻的反向旋转 - 玻璃层和晶片边缘处的聚合物,以完成层间电介质夹心层。 覆盖在夹层上的光致抗蚀剂层,其中光致抗蚀剂层不比第三距离更靠近晶片边缘延伸,并被图案化以形成光致抗蚀剂掩模。 蚀刻掉层间电介质夹层,其中它不被掩模覆盖,以形成通孔,其中覆盖聚合物的第二氧化物层被蚀刻掉。 剥离光致抗蚀剂掩模,由此聚合物​​也被除去,从而避免在晶片边缘处的氧化物剥离。