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    Enhanced dynamic address translation with load real address function
    1.
    发明授权
    Enhanced dynamic address translation with load real address function 失效
    增强动态地址转换与负载实地址功能

    公开(公告)号：US08041922B2

    公开(公告)日：2011-10-18

    申请号：US11972705

    申请日：2008-01-11

    申请人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F12/02

    CPC分类号： G06F12/1009 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/34 ,  G06F9/342 ,  G06F2212/651 ,  G06F2212/657

    摘要： What is provided is a load real address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction containing an opcode is obtained indicating that a load real address is to be performed. The instruction further identifies a first general register. Based on the contents of the machine instruction, a virtual address to be translated is obtained. Dynamic address translation is performed on the virtual address to obtain a segment-frame absolute address of a large block of data in memory. If an extended DAT facility and a format control field in the segment table entry are enabled, the address of the block of data is saved in the first general register. A page index portion and a byte index portion of the virtual address may also be saved in the first general register.

    摘要翻译： 提供了为计算机系统的机器结构定义的负载实地址功能。 在一个实施例中，获得包含操作码的机器指令，指示要执行负载实际地址。 该指令进一步标识第一个通用寄存器。 根据机器指令的内容，获得要翻译的虚拟地址。 对虚拟地址执行动态地址转换，以获得存储器中大块数据的段帧绝对地址。 如果分段表项中的扩展DAT功能和格式控制字段被使能，数据块的地址将保存在第一个通用寄存器中。 虚拟地址的页索引部分和字节索引部分也可以保存在第一通用寄存器中。

    DYNAMIC ADDRESS TRANSLATION WITH LOAD PAGE TABLE ENTRY ADDRESS
    2.
    发明申请
    DYNAMIC ADDRESS TRANSLATION WITH LOAD PAGE TABLE ENTRY ADDRESS 有权
    动态地址转换与加载页表输入地址

    公开(公告)号：US20090182975A1

    公开(公告)日：2009-07-16

    申请号：US11972700

    申请日：2008-01-11

    申请人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F12/1009 ,  G06F2212/651 ,  G06F2212/652

    摘要： What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.

    摘要翻译： 提供了为计算机系统的机器结构定义的加载页表项地址函数。 在一个实施例中，获得机器指令，其中包含指示要执行加载页表项地址函数的操作码。 机器指令包含M字段，标识第一通用寄存器的第一字段和标识第二通用寄存器的第二字段。 基于M场的内容，获得具有至少一个段表的地址转换表的层次结构的初始起始地址。 基于获得的初始起始地址，执行动态地址转换，直到获得页表项。 页表入口地址保存在识别的第一个通用寄存器中。

    DYNAMIC ADDRESS TRANSLATION WITH LOAD REAL ADDRESS
    3.
    发明申请
    DYNAMIC ADDRESS TRANSLATION WITH LOAD REAL ADDRESS 失效
    动态地址翻译与负载实地址

    公开(公告)号：US20090182973A1

    公开(公告)日：2009-07-16

    申请号：US11972705

    申请日：2008-01-11

    申请人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F9/34

    CPC分类号： G06F12/1009 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/34 ,  G06F9/342 ,  G06F2212/651 ,  G06F2212/657

    摘要： What is provided is a load real address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction containing an opcode is obtained indicating that a load real address is to be performed. The instruction further identifies a first general register. Based on the contents of the machine instruction, a virtual address to be translated is obtained. Dynamic address translation is performed on the virtual address to obtain a segment-frame absolute address of a large block of data in memory. If an extended DAT facility and a format control field in the segment table entry are enabled, the address of the block of data is saved in the first general register. A page index portion and a byte index portion of the virtual address may also be saved in the first general register.

    摘要翻译： 提供了为计算机系统的机器结构定义的负载实地址功能。 在一个实施例中，获得包含操作码的机器指令，指示要执行负载实际地址。 该指令进一步标识第一个通用寄存器。 根据机器指令的内容，获得要翻译的虚拟地址。 对虚拟地址执行动态地址转换，以获得存储器中大块数据的段帧绝对地址。 如果分段表项中的扩展DAT功能和格式控制字段被使能，数据块的地址将保存在第一个通用寄存器中。 虚拟地址的页索引部分和字节索引部分也可以保存在第一通用寄存器中。

    Load Page Table Entry Address Instruction Execution Based on an Address Translation Format Control Field
    4.
    发明申请
    Load Page Table Entry Address Instruction Execution Based on an Address Translation Format Control Field 有权
    基于地址转换格式控制字段加载页表输入地址指令执行

    公开(公告)号：US20120011341A1

    公开(公告)日：2012-01-12

    申请号：US13234374

    申请日：2011-09-16

    申请人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F12/1009 ,  G06F2212/651 ,  G06F2212/652

    摘要： What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.

    摘要翻译： 提供了为计算机系统的机器结构定义的加载页表项地址函数。 在一个实施例中，获得机器指令，其中包含指示要执行加载页表项地址函数的操作码。 机器指令包含M字段，标识第一通用寄存器的第一字段和标识第二通用寄存器的第二字段。 基于M场的内容，获得具有至少一个分段表的地址转换表的层次结构的初始起始地址。 基于获得的初始起始地址，执行动态地址转换，直到获得页表项。 页表入口地址保存在识别的第一个通用寄存器中。

    Load page table entry address instruction execution based on an address translation format control field
    5.
    发明授权
    Load page table entry address instruction execution based on an address translation format control field 有权
    基于地址转换格式控制字段加载页表项目地址指令执行

    公开(公告)号：US08041923B2

    公开(公告)日：2011-10-18

    申请号：US11972700

    申请日：2008-01-11

    申请人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F12/1027 ,  G06F12/1009 ,  G06F2212/651 ,  G06F2212/652

    摘要： What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.

    摘要翻译： 提供了为计算机系统的机器结构定义的加载页表项地址函数。 在一个实施例中，获得机器指令，其中包含指示要执行加载页表项地址函数的操作码。 机器指令包含M字段，标识第一通用寄存器的第一字段和标识第二通用寄存器的第二字段。 基于M场的内容，获得具有至少一个段表的地址转换表的层次结构的初始起始地址。 基于获得的初始起始地址，执行动态地址转换，直到获得页表项。 页表入口地址保存在识别的第一个通用寄存器中。

    DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT
    6.
    发明申请
    DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT 有权
    动态地址翻译与框架管理

    公开(公告)号：US20090187724A1

    公开(公告)日：2009-07-23

    申请号：US11972725

    申请日：2008-01-11

    申请人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1475 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30145 ,  G06F12/10

    摘要： What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block.

    摘要翻译： 公开的是针对计算机系统的机器结构定义的集合关键和清晰的帧管理功能。 在一个实施例中，获得识别第一和第二通用寄存器的机器指令。 从第一通用寄存器获得的是指示存储帧是小块还是大块数据的帧大小字段。 从第二通用寄存器获得的是要执行指令的存储帧的操作数地址。 如果存储帧是小块，则仅在小块上执行指令。 如果指示的存储帧是大数据块，则从第二通用寄存器获得大数据块内的初始第一数据块的操作数地址。 在从初始第一块开始的所有块上执行帧管理指令。

    Perform frame management function instruction for clearing blocks of main storage
    7.
    发明授权
    Perform frame management function instruction for clearing blocks of main storage 有权
    执行清理主存储块的帧管理功能指令

    公开(公告)号：US08335906B2

    公开(公告)日：2012-12-18

    申请号：US11972718

    申请日：2008-01-11

    申请人： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1036 ,  G06F9/30043 ,  G06F9/30145

    摘要： What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained containing an opcode for a frame management instruction identifying a first and second general register. Clear frame information is obtained from the first general register having a frame size field indicating whether a storage frame is a small or large block of data. The second general register contains an operand address of a storage frame. If the storage frame is a small block, all bytes of the small block of data are set to zero. If the storage frame is a large block of data, an operand address of an initial first block of data within the large block is obtained from the second general register. All data of all blocks within the large block are cleared starting from the initial first block.

    摘要翻译： 公开的是针对计算机系统的机器结构定义的帧管理功能。 在一个实施例中，获得包含识别第一和第二通用寄存器的帧管理指令的操作码的机器指令。 从具有指示存储帧是小数据块还是大数据块的帧大小字段的第一通用寄存器获得清除帧信息。 第二个通用寄存器包含存储帧的操作数地址。 如果存储帧是小块，则小块数据的所有字节都被设置为零。 如果存储帧是大数据块，则从第二通用寄存器获得大块内的初始第一数据块的操作数地址。 大块内的所有块的所有数据从初始第一块开始清零。

    Dynamic address translation with frame management
    9.
    发明授权
    Dynamic address translation with frame management 有权
    动态地址转换与帧管理

    公开(公告)号：US08151083B2

    公开(公告)日：2012-04-03

    申请号：US11972713

    申请日：2008-01-11

    申请人： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1475 ,  G06F9/30003 ,  G06F9/3004 ,  G06F9/30145 ,  G06F12/00 ,  G06F12/023 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/145 ,  G06F2212/68

    摘要： What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.

    摘要翻译： 公开的是针对计算机系统的机器结构定义的帧管理功能。 在一个实施例中，获得识别第一和第二通用寄存器的帧管理指令。 第一通用寄存器包含具有带有访问保护位的密钥字段和块大小指示的帧管理字段。 如果块大小指示指示大块，则从第二通用寄存器获得大数据块的操作数地址。 大块数据具有多个小块，每个小块与具有多个存储密钥访问保护位的对应存储密钥相关联。 如果块大小指示指示大块，则使用密钥字段的访问保护位来设置大块内的每个小块的每个相应的存储密钥的存储密钥访问保护位。

    DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT
    10.
    发明申请
    DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT 有权
    动态地址翻译与框架管理

    公开(公告)号：US20090193214A1

    公开(公告)日：2009-07-30

    申请号：US11972718

    申请日：2008-01-11

    申请人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1036 ,  G06F9/30043 ,  G06F9/30145

    摘要： What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained containing an opcode for a frame management instruction identifying a first and second general register. Clear frame information is obtained from the first general register having a frame size field indicating whether a storage frame is a small or large block of data. The second general register contains an operand address of a storage frame. If the storage frame is a small block, all bytes of the small block of data are set to zero. If the storage frame is a large block of data, an operand address of an initial first block of data within the large block is obtained from the second general register. All data of all blocks within the large block are cleared starting from the initial first block.

    摘要翻译： 公开的是针对计算机系统的机器结构定义的帧管理功能。 在一个实施例中，获得包含识别第一和第二通用寄存器的帧管理指令的操作码的机器指令。 从具有指示存储帧是小数据块还是大数据块的帧大小字段的第一通用寄存器获得清除帧信息。 第二个通用寄存器包含存储帧的操作数地址。 如果存储帧是小块，则小块数据的所有字节都被设置为零。 如果存储帧是大数据块，则从第二通用寄存器获得大块内的初始第一数据块的操作数地址。 大块内的所有块的所有数据从初始第一块开始清零。