公开(公告)号：US20210159911A1

公开(公告)日：2021-05-27

申请号：US17098711

申请日：2020-11-16

Applicant: DENSO CORPORATION

Inventor： Kunihiko NAKAMURA ,  Tomohiro NEZUKA

IPC: H03M3/00 ,  H03M1/46 ,  H03M1/36 ,  G06G7/186

Abstract: An A/D converter includes: a sampler that includes a sampling capacitor and samples an input signal; a D/A converter that selectively outputs an analog voltage; an integrator that integrates an input from the sampler and an input from the D/A converter; Multiple switches that include a first switch independently connecting the sampler to the integrator, a second switch independently connecting the D/A converter to the integrator, a third switch, and, a fourth switch, a quantizer that quantizes an output of the integrator; a control circuit that outputs a digital value based on an output of the quantizer, and a reference potential generation circuit that provides a second reference potential to an integrator side of the sampler through the third switch and provides a first reference potential to the integrator side of the D/A converter through the fourth switch.

公开(公告)号：US20210075438A1

公开(公告)日：2021-03-11

申请号：US16937804

申请日：2020-07-24

Applicant: DENSO CORPORATION

Inventor： Kunihiko NAKAMURA ,  Tomohiro NEZUKA ,  Kazutaka HONDA

IPC: H03M3/00 ,  H03M1/14

Abstract: An A/D conversion device, which operates in one mode including at least one of a ΔΣ mode, a cyclic mode, and a hybrid mode, includes: a first block that processes an analog input signal by a first amplifier; a second block including a second amplifier; a quantization unit that quantizes one of outputs of the first and second blocks; and a control circuit that switches the mode to perform a control corresponding to the mode.

公开(公告)号：US20200162093A1

公开(公告)日：2020-05-21

申请号：US16596927

申请日：2019-10-09

Applicant: DENSO CORPORATION

Inventor： Kunihiko NAKAMURA ,  Yu FUJIMOTO ,  Tomohiro NEZUKA

IPC: H03M1/12 ,  H03M1/14 ,  H03M1/46 ,  H03M1/68 ,  H03M1/80

Abstract: An input signal Vin is sampled, when a first terminal of a sampling capacitor is connected to a node and a second terminal of the sampling capacitor is connected to an analog ground. A charge transfer operation is performed, when the first terminal of the sampling capacitor is connected to the analog ground and the second terminal of the sampling capacitor is connected to an inverting input terminal of an operational amplifier. A quantization is performed, when an output of the operational amplifier is input to a quantizer. Most significant bits are generated by repeating a subtraction operation in which a charge subtraction unit subtracts a charge accumulated in the integration capacitor based on a quantization result a predetermined number of times. Least significant bits are generated when a voltage provided by amplifying a voltage corresponding to a charge remaining in the integration capacitor is input to a sub-A/D converter after generation of the most significant bits. A sum of the most significant bits and the least significant bits are output as an output signal. Initialization of the charge of the integration capacitor, the charge transfer operation for a next A/D conversion, and generation of the most significant bits are performed in parallel with the A/D conversion in the sub-A/D converter after the generation of the most significant bits.

公开(公告)号：US20200153446A1

公开(公告)日：2020-05-14

申请号：US16594587

申请日：2019-10-07

Applicant: DENSO CORPORATION

Inventor： Kunihiko NAKAMURA ,  Tomohiro NEZUKA

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/36

Abstract: A ΔΣ modulator includes an input circuit having a sampling capacitor, an integration circuit, a quantizer and a D/A converter having a DAC capacitor. The input circuit takes in an analog input voltage in the sampling capacitor in a sampling period, and transfers a charge to the integration circuit in a holding period. The D/A converter takes in an analog potential, to which selection switches are connected in the sampling period based on a digital output of the quantizer, in the DAC capacitor, and subtracts a charge from the integration circuit in the holding period. At this time, since the input circuit and the D/A converter are set so that the holding periods do not overlap with each other, an error caused by the lowering of a feedback factor is suppressed.

公开(公告)号：US20200112318A1

公开(公告)日：2020-04-09

申请号：US16555042

申请日：2019-08-29

Applicant: DENSO CORPORATION

Inventor： Kunihiko NAKAMURA ,  Tomohiro NEZUKA

IPC: H03M1/36 ,  H03M1/46 ,  H03M1/66 ,  H03M3/00

Abstract: A D/A conversion circuit includes: an output terminal connected to an operational amplifier connected to a quantization circuit; a DAC capacitor; a selection switch switching among reference, first and second voltages to apply to the DAC capacitor as an analog potential; a ground switch connecting the DAC capacitor to a ground; and an output switch connecting the DAC capacitor to the output terminal. In a first period, the selection switch selects one of the reference, first and second voltages according to a quantization result value from the quantization circuit, and connects the one to the DAC capacitor, and the ground switch turns on to charge the DAC capacitor. In a second period, the selection switch selects another one of the first and second voltages, and connects the another one to the DAC capacitor, and the output switch turns on to output the analog potential to the output terminal.