公开(公告)号：US20250102545A1

公开(公告)日：2025-03-27

申请号：US18825286

申请日：2024-09-05

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： Shogo KAWAHARA ,  Yoshikazu FURUTA ,  Tomohiro NEZUKA

IPC: G01R19/00 ,  G01R1/20

Abstract: A shunt-based current sensor executes redundancy detection of a load current flowing through a load by using a shunt resistor. The shunt-based current sensor includes a reference resistor, a current excitation circuit, at least two voltage measurement circuits and a signal processing circuit. The reference resistor is connected to the shunt resistor in series. The current excitation circuit generates an AC excitation current and supply the AC excitation current to the shunt resistor and the reference resistor. At least two voltage measurement circuits measure a voltage across the shunt resistor. A signal processing circuit executes signal processing based on respective measurement voltages of the at least two voltage measurement circuits, and is operated in the load current redundancy detection mode or a shunt resistance measurement mode.

公开(公告)号：US20210013876A1

公开(公告)日：2021-01-14

申请号：US17036366

申请日：2020-09-29

Applicant: DENSO CORPORATION

Inventor： Shogo KAWAHARA

IPC: H03K17/00 ,  H03G1/00 ,  H03F3/45 ,  H03K17/693

Abstract: First switches are respectively connected between multiple input terminals and an inverting input of an operational amplifier. Second switches and feedback resistors are respectively sequentially series-connected between an output of the operational amplifier and nodes between the multiple input terminals and the first switches. Third switches are respectively connected between nodes between the second switches and the feedback resistors and an output terminal of an amplification circuit with an analog multiplexer.

公开(公告)号：US20190154519A1

公开(公告)日：2019-05-23

申请号：US16300072

申请日：2017-08-29

Applicant: DENSO CORPORATION

Inventor： Shogo KAWAHARA

IPC: G01K7/24 ,  G01R19/165

Abstract: In a configuration for measuring a signal voltage by a voltage measuring unit through a multiplexer to which signals are inputted from a plurality of sensors including a thermistor, a series circuit which includes the thermistor, a driving resistor and a level shift resistor is connected between a power supply and the ground. A common connection point between the driving resistor and the level shift resistor is connected to an input terminal of the multiplexer.

公开(公告)号：US20210391838A1

公开(公告)日：2021-12-16

申请号：US17458892

申请日：2021-08-27

Applicant: DENSO CORPORATION

Inventor： Shogo KAWAHARA

IPC: H03F3/45

Abstract: A switched-capacitor amplifier includes a sampling capacitor, a first switch, a differential amplifier, a reference power supply, a second switch, a third switch, and a controller configured to execute on and off control of the first to third switches. The second switch includes a series circuit of first and second metal oxide semiconductor (MOS) transistors and a potential holding capacitor connected between a node that is a common connection point of the first and second MOS transistors and a ground.

公开(公告)号：US20160261276A1

公开(公告)日：2016-09-08

申请号：US14994564

申请日：2016-01-13

Applicant: DENSO CORPORATION

Inventor： Shogo KAWAHARA ,  Tomohiro NEZUKA

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/08 ,  H03M1/765

Abstract: A D/A converter is configured to output tri-level potentials from an output terminal. A high potential terminal and the output terminal are connected through a p-type MOS transistor. An intermediate potential terminal and the output terminal are connected through p-type and n-type MOS transistors, which are connected in series and have low threshold voltages. A low potential terminal and the output terminal are connected through an n-type MOS transistor. The p-type MOS transistor and the n-type MOS transistor connected to the intermediate potential terminal have a positive voltage and a negative voltage between gate-source paths in off-states, respectively, and a substrate bias effect and hence remain in the off-state stably.

Abstract translation: D / A转换器被配置为从输出端子输出三电平电位。 高电位端子和输出端子通过p型MOS晶体管连接。 中间电位端子和输出端子通过串联连接并具有低阈值电压的p型和n型MOS晶体管连接。 低电位端子和输出端子通过n型MOS晶体管连接。 连接到中间电位端子的p型MOS晶体管和n型MOS晶体管分别在截止状态下的栅极 - 源极之间具有正电压和负电压以及衬底偏置效应，因此保持在截止状态 状态稳定。

公开(公告)号：US20220239258A1

公开(公告)日：2022-07-28

申请号：US17577970

申请日：2022-01-18

Applicant: DENSO CORPORATION

Inventor： Shogo KAWAHARA ,  Tetsuya MAKIHARA ,  Takeshi MORINAGA

IPC: H03F1/02 ,  H03F3/16

Abstract: An amplifier circuit includes a main amplifier and an auxiliary circuit that improves a slew rate of the main amplifier. The main amplifier is composed of a one-stage CMOS amplifier, amplifies a voltage difference between two input signals, and outputs, from output terminals, an output signal corresponding to the voltage difference of the input signals. The auxiliary circuit controls an auxiliary bias current flowing through the output terminals according to the voltage difference of the input signals, and interrupts the auxiliary bias current at a predetermined timing before completion of settling. Such a scheme enables improvement of a slew rate by the auxiliary circuit and high-speed operation as well as reduction of error due to mismatch between the main amplifier and the auxiliary circuit, thereby yielding high-accuracy output signal output therefrom.

公开(公告)号：US20160373107A1

公开(公告)日：2016-12-22

申请号：US15078013

申请日：2016-03-23

Applicant: DENSO CORPORATION

Inventor： Shogo KAWAHARA ,  Tomohiro NEZUKA

IPC: H03K17/693

CPC classification number: H03K17/693 ,  H03M1/00 ,  H03M3/464

Abstract: First and second p-type transistors are connected in series between an output terminal and a positive power terminal. First and second n-type transistors are connected in series between a node and a negative power terminal. A third p-type transistor is connected between a node and the positive power terminal. Third and fourth n-type transistors are connected in series between the output terminal and a low potential terminal. Fourth and fifth p-type transistors are connected in series between a node and the negative power terminal. A fifth n-type transistor is connected between a node and the negative power terminal. A high potential is outputted without leak current when the first to fifth p-type transistors are turned on and the first to fifth n-type transistors are turned off.

Abstract translation: 第一和第二p型晶体管串联连接在输出端子和正电源端子之间。 第一和第二n型晶体管串联在节点和负电源端子之间。 第三个p型晶体管连接在节点和正电源端子之间。 第三和第四n型晶体管串联在输出端子和低电位端子之间。 第四和第五p型晶体管串联连接在节点和负电源端子之间。 第五个n型晶体管连接在节点和负电源端子之间。 当第一至第五p型晶体管导通并且第一至第五n型晶体管截止时，无泄漏电流输出高电位。