公开(公告)号：US10777545B2

公开(公告)日：2020-09-15

申请号：US16377563

申请日：2019-04-08

申请人： DENSO CORPORATION

发明人： Akira Yamada ,  Shinya Sakurai ,  Takashi Nakano ,  Yosuke Kondo ,  Mutsuya Motojima

IPC分类号： H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/8222 ,  H01L27/08 ,  H01L21/822 ,  H01L27/06 ,  H01L27/04 ,  H01L27/088

摘要： A semiconductor device configures a protection element that protects a protection target element connected between a cathode electrode and an anode electrode when a parasitic transistor configured by a cathode region, a first conductivity type well layer, and a second conductivity type well is turned on and electrical continuity is established between the cathode electrode and the anode electrode. The semiconductor device includes a plurality of body regions in one cell of the protection element, and the plurality of body regions is brought in contact with the cathode electrode.

公开(公告)号：US10026663B2

公开(公告)日：2018-07-17

申请号：US15515212

申请日：2015-11-13

申请人： DENSO CORPORATION

发明人： Kouji Eguchi ,  Takashi Nakano

IPC分类号： H01L21/66 ,  H01L21/78 ,  H01L21/02

摘要： A semiconductor device manufacturing method is provided. In a semiconductor wafer prepared, the width of a dicing line is larger than a cut region to be diced with a dicing blade, a first chip forming region and a second chip forming region are adjacent and have the dicing line therebetween, some of the pads are formed on a first chip forming region side, and the remaining pads are formed on a second chip forming region side. The semiconductor wafer is diced with the dicing blade in such manner that, when the some of the pads are diced, a part of the dicing blade on the second chip forming region side does not abut the some of the pads, and, when the remaining pads are diced, a part of the dicing blade on the first one chip forming region side does not abut the remaining pads.

公开(公告)号：US08907422B2

公开(公告)日：2014-12-09

申请号：US13951644

申请日：2013-07-26

申请人： DENSO CORPORATION

发明人： Syunsuke Harada ,  Takashi Nakano ,  Takuya Okuno

IPC分类号： H01L29/78

CPC分类号： H01L29/0878 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/7394 ,  H01L29/7824

摘要： A semiconductor device includes: a semiconductor substrate including a first semiconductor layer on the semiconductor substrate; multiple semiconductor elements in the semiconductor substrate; and an ineffective region. Each semiconductor element includes: a second semiconductor layer in a surface portion of the first semiconductor layer; a third semiconductor layer disposed in another surface portion of the first semiconductor layer and spaced a part from the second semiconductor layer; and a control layer disposed on a portion of the first semiconductor layer between the second semiconductor layer and the third semiconductor layer. The ineffective region is disposed in the semiconductor substrate between at least two adjacent semiconductor elements; and does not provide a function of the semiconductor elements.

摘要翻译： 半导体器件包括：半导体衬底，其包括半导体衬底上的第一半导体层; 半导体衬底中的多个半导体元件; 和一个无效的地区。 每个半导体元件包括：第一半导体层的表面部分中的第二半导体层; 第三半导体层，设置在所述第一半导体层的另一表面部分中，并与所述第二半导体层间隔一部分; 以及控制层，设置在第二半导体层和第三半导体层之间的第一半导体层的一部分上。 无效区域设置在半导体衬底中的至少两个相邻的半导体元件之间; 并且不提供半导体元件的功能。

公开(公告)号：US10854543B2

公开(公告)日：2020-12-01

申请号：US15502244

申请日：2015-10-02

申请人： DENSO CORPORATION

发明人： Shin Takizawa ,  Takashi Nakano

IPC分类号： H01L23/522 ,  H01L27/01 ,  H01C7/00 ,  H01L27/08 ,  H01L27/10 ,  H01L49/02 ,  H01L23/00

摘要： A semiconductor device includes: a substrate; a first wiring layer arranged above the substrate; a first insulating film covering the first wiring layer; a lower oxidation preventing film arranged on the first insulating film; at least one thin-film resistor arranged on the lower oxidation preventing film; an upper oxidation preventing film arranged on the at least one thin-film resistor; a second insulating film covering the lower oxidation preventing film, the at least one thin-film resistor, and the upper oxidation preventing film; a second wiring layer arranged on the second insulating film; and a third insulating film covering the second wiring layer. The first wiring layer overlaps an end portion of the at least one thin-film resistor when viewed in a normal direction of one surface of the substrate.