公开(公告)号：US09154175B2

公开(公告)日：2015-10-06

申请号：US14134338

申请日：2013-12-19

申请人： DENSO CORPORATION ,  ANDEN CO., LTD.

发明人： Hideki Kashima ,  Tomohisa Kishigami ,  Naoji Kaneko ,  Nobutomo Takagi

IPC分类号： H04B1/40 ,  B60R16/03 ,  H04L25/49 ,  H04L12/403 ,  H04J3/06 ,  H04L12/40

CPC分类号： H04B1/40 ,  B60R16/03 ,  H04J3/0697 ,  H04L7/033 ,  H04L12/4035 ,  H04L25/03834 ,  H04L25/4902 ,  H04L2012/40215 ,  H04L2012/40273

摘要： A transceiver that transmits and receives data used in a communication system, in which the data is encoded by a transmission line code and a signal level of the transmission code changes at a predetermined transition timing in a bit-duration. The transceiver includes: a clock generator that generates an internal clock used for internal circuits; a timing generator that generates, by using the internal clock generated by the clock generator, a timing signal synchronized to a reference clock supplied externally; an encoding circuit that encodes, by using the timing signal generated by the timing generator, a transmission data which is synchronized to the reference clock to be the transmission line code; and a waveform shaping unit that performs a waveform shaping of a waveform at the predetermined transition timing of the transmission data to be based on the reference clock.

摘要翻译： 发送和接收在通信系统中使用的数据的收发器，其中数据由传输线码编码，并且传输码的信号电平在比特持续时间内在预定的转换定时改变。 收发器包括：产生用于内部电路的内部时钟的时钟发生器; 定时发生器，其通过使用由时钟发生器产生的内部时钟产生与外部提供的参考时钟同步的定时信号; 编码电路，通过使用由定时发生器产生的定时信号，将与基准时钟同步的发送数据编码为传输线路码; 以及波形整形单元，其基于所述参考时钟在所述发送数据的所述预定转换定时处执行波形的波形整形。

公开(公告)号：US09094279B2

公开(公告)日：2015-07-28

申请号：US14083814

申请日：2013-11-19

申请人： DENSO CORPORATION ,  ANDEN CO., LTD.

发明人： Hideki Kashima ,  Tomohisa Kishigami ,  Naoji Kaneko ,  Nobutomo Takagi

IPC分类号： H03K7/08 ,  H04L25/49 ,  H04L7/04 ,  H04L7/06

CPC分类号： H04L25/4902 ,  H04L7/041 ,  H04L7/065

摘要： A communication apparatus includes a detecting unit, a process performing unit, and a range setting unit. The detecting unit detects a boundary pattern periodically appearing between codes in a binary coded signal transmitted through a transmission line. The boundary pattern is information showing a boundary appearing between codes. The process performing unit performs a process in synchronization with timing of appearance of the boundary pattern. The range setting unit sets an allowance range which is set include timing at which it is estimated that the next boundary pattern appears. The timing is counted from the timing currently detected by the detecting unit. The detecting unit includes a section which detects the timing of appearance of the boundary pattern during the allowance range.

摘要翻译： 通信装置包括检测单元，处理执行单元和范围设置单元。 检测单元检测通过传输线传输的二进制编码信号中的码之间周期性出现的边界模式。 边界模式是显示代码之间出现边界的信息。 处理执行单元与边界图案的出现定时同步地执行处理。 范围设定单元设定允许范围，包括估计下一个边界图案出现的定时。 定时从检测单元当前检测到的定时开始计数。 检测单元包括在容许范围内检测边界图案的出现定时的部分。

公开(公告)号：US20140036987A1

公开(公告)日：2014-02-06

申请号：US13954069

申请日：2013-07-30

申请人： DENSO CORPORATION

发明人： Hideki Kashima ,  Tomohisa Kishigami ,  Naoji Kaneko

IPC分类号： H03K7/08

CPC分类号： H03K7/08

摘要： A decoder for decoding an input signal coded with a pulse width modulation code as a line code to an output signal in a binary code, has a first memory, a first timer, a determination circuit and a first controller. The information on a duty duration of the PWM code, corresponding to at least one kind of the output signals, is stored on the first memory. The first timer has a capacity to measure the duty duration of the input signal. The determination circuit has a capacity to determining which kind of the output signals corresponds to the input signal, on the basis of the information stored on the first memory and the duty duration measured with the first timer. The first controller has a capacity to updating the information stored on the first memory, on the basis of the determination result and the measured duty duration.

摘要翻译： 将以脉冲宽度调制码编码的输入信号解码为二进制码中的输出信号的行码的解码器具有第一存储器，第一定时器，确定电路和第一控制器。 对应于至少一种输出信号的PWM代码的占空比持续时间的信息被存储在第一存储器上。 第一定时器具有测量输入信号占空比的能力。 确定电路具有根据存储在第一存储器上的信息和用第一定时器测量的占空比来确定哪种输出信号对应于输入信号的能力。 第一控制器具有根据确定结果和测量的占空比持续时间来更新存储在第一存储器上的信息的能力。

公开(公告)号：US10305672B2

公开(公告)日：2019-05-28

申请号：US16051661

申请日：2018-08-01

申请人： DENSO CORPORATION

发明人： Naoji Kaneko ,  Takamori Ookawa

IPC分类号： H04L7/00 ,  H04L25/49 ,  H04J3/06

摘要： A communication system includes a master node and one more slave nodes connected via a transmission line. The master node is configured to output a first PWM signal having a shorter low level time and a second PWM signal having a longer low level time. The slave node is configured to output the second PWM signal when detecting a high to low signal level change on the transmission line. The master node detects a time delay as measured from when an input signal to a transmission buffer falls to when an output signal from a reception buffer falls. The time delay is an index value used to change the low level time of the first PWM signal when the time delay is equal to or less than a preset value.

公开(公告)号：US09130551B2

公开(公告)日：2015-09-08

申请号：US13954069

申请日：2013-07-30

申请人： DENSO CORPORATION

发明人： Hideki Kashima ,  Tomohisa Kishigami ,  Naoji Kaneko

IPC分类号： H03K9/08 ,  H03K7/08

CPC分类号： H03K7/08

摘要： A decoder for decoding an input signal coded with a pulse width modulation code as a line code to an output signal in a binary code, has a first memory, a first timer, a determination circuit and a first controller. The information on a duty duration of the PWM code, corresponding to at least one kind of the output signals, is stored on the first memory. The first timer has a capacity to measure the duty duration of the input signal. The determination circuit has a capacity to determining which kind of the output signals corresponds to the input signal, on the basis of the information stored on the first memory and the duty duration measured with the first timer. The first controller has a capacity to updating the information stored on the first memory, on the basis of the determination result and the measured duty duration.

摘要翻译： 将以脉冲宽度调制码编码的输入信号解码为二进制码中的输出信号的行码的解码器具有第一存储器，第一定时器，确定电路和第一控制器。 对应于至少一种输出信号的PWM代码的占空比持续时间的信息被存储在第一存储器上。 第一定时器具有测量输入信号占空比的能力。 确定电路具有根据存储在第一存储器上的信息和用第一定时器测量的占空比来确定哪种输出信号对应于输入信号的能力。 第一控制器具有根据确定结果和测量的占空比持续时间来更新存储在第一存储器上的信息的能力。

公开(公告)号：US08929431B2

公开(公告)日：2015-01-06

申请号：US13954089

申请日：2013-07-30

申请人： Denso Corporation

发明人： Hideki Kashima ,  Tomohisa Kishigami ,  Naoji Kaneko

IPC分类号： H03K7/08 ,  H04L25/49

CPC分类号： H04L25/4902

摘要： Serial data are transmitted between transceivers via a communication path, each bit expressed by a dominant code or a recessive code which vary between dominant and recessive levels, the dominant code having a greater proportion of duration at the dominant level. A device (clock master) can continuously output successive recessive codes to the communication path, in which condition a transceiver can transmit a dominant code by producing an output drive signal which overwrites a part of a recessive code, currently being received from the communication path, to the dominant level. The output drive signal is shaped with a steeper edge slope at a transition from an inactive to an active level than from the active to the inactive level, enabling an increased data transmission rate without increased noise.

摘要翻译： 串行数据经由通信路径在收发器之间传输，每个位由主导代码或隐性代码表示，隐性代码在主导和隐性级别之间变化，主导代码在主导级别具有较大比例的持续时间。 一个设备（时钟主机）可以将连续的隐性代码连续地输出到通信路径，在这种情况下，收发器可以通过产生覆盖当前从通信路径接收的隐性代码的一部分的输出驱动信号来发送主导代码， 达到主导地位。 输出驱动信号在从非活动电平到从有源电平转换到无效电平的转换时具有更陡峭的边沿斜率，从而能够提高数据传输速率而不增加噪声。

公开(公告)号：US20140036988A1

公开(公告)日：2014-02-06

申请号：US13954089

申请日：2013-07-30

申请人： DENSO CORPORATION

发明人： Hideki Kashima ,  Tomohisa Kishigami ,  Naoji Kaneko

IPC分类号： H04L25/49

CPC分类号： H04L25/4902

摘要： Serial data are transmitted between transceivers via a communication path, each bit expressed by a dominant code or a recessive code which vary between dominant and recessive levels, the dominant code having a greater proportion of duration at the dominant level. A device (clock master) can continuously output successive recessive codes to the communication path, in which condition a transceiver can transmit a dominant code by producing an output drive signal which overwrites a part of a recessive code, currently being received from the communication path, to the dominant level. The output drive signal is shaped with a steeper edge slope at a transition from an inactive to an active level than from the active to the inactive level, enabling an increased data transmission rate without increased noise.

摘要翻译： 串行数据经由通信路径在收发器之间传输，每个位由主导代码或隐性代码表示，隐性代码在主导和隐性级别之间变化，主导代码在主导级别具有较大比例的持续时间。 一个设备（时钟主机）可以将连续的隐性代码连续地输出到通信路径，在这种情况下，收发器可以通过产生覆盖当前从通信路径接收的隐性代码的一部分的输出驱动信号来发送主导代码， 达到主导地位。 输出驱动信号在从非活动电平到从有源电平转换到无效电平的转换时具有更陡峭的边沿斜率，从而能够提高数据传输速率而不增加噪声。