公开(公告)号：US20120146017A1

公开(公告)日：2012-06-14

申请号：US13324751

申请日：2011-12-13

申请人： Dae-Hwan KIM ,  Byung-Kook Choi ,  Sul Lee ,  Hoon Yim

发明人： Dae-Hwan KIM ,  Byung-Kook Choi ,  Sul Lee ,  Hoon Yim

IPC分类号： H01L33/08 ,  H01L21/34

CPC分类号： H01L29/7869 ,  H01L27/1225

摘要： A method for fabricating an oxide thin film transistor includes sequentially forming a gate insulating film, an oxide semiconductor layer, and a first insulating layer; selectively patterning the oxide semiconductor layer and the first insulating layer to form an active layer and an insulating layer pattern on the gate electrode; forming a second insulating layer on the substrate having the active layer and the insulating layer pattern formed thereon; and selectively patterning the insulating layer pattern and the second insulating layer to form first and second etch stoppers on the active layer. The oxide semiconductor layer may be a ternary system or quaternary system oxide semiconductor comprising a combination of AxByCzO (A, B, C═Zn, Cd, Ga, In, Sn, Hf, Zr; x, y, z≧0).

摘要翻译： 一种制造氧化物薄膜晶体管的方法，包括顺序地形成栅极绝缘膜，氧化物半导体层和第一绝缘层; 选择性地图案化氧化物半导体层和第一绝缘层以在栅电极上形成有源层和绝缘层图案; 在其上形成有活性层和绝缘层图案的基板上形成第二绝缘层; 以及选择性地图案化所述绝缘层图案和所述第二绝缘层以在所述有源层上形成第一和第二蚀刻阻挡层。 氧化物半导体层可以是包含AxByCzO（A，B，C = Zn，Cd，Ga，In，Sn，Hf，Zr; x，y，z≥0）的组合的三元系或四元系氧化物半导体。

公开(公告)号：US08735883B2

公开(公告)日：2014-05-27

申请号：US13324751

申请日：2011-12-13

申请人： Dae-Hwan Kim ,  Byung-Kook Choi ,  Sul Lee ,  Hoon Yim

发明人： Dae-Hwan Kim ,  Byung-Kook Choi ,  Sul Lee ,  Hoon Yim

IPC分类号： H01L29/10 ,  H01L29/786 ,  H01L27/12

CPC分类号： H01L29/7869 ,  H01L27/1225

摘要： A method for fabricating an oxide thin film transistor includes sequentially forming a gate insulating film, an oxide semiconductor layer, and a first insulating layer; selectively patterning the oxide semiconductor layer and the first insulating layer to form an active layer and an insulating layer pattern on the gate electrode; forming a second insulating layer on the substrate having the active layer and the insulating layer pattern formed thereon; and selectively patterning the insulating layer pattern and the second insulating layer to form first and second etch stoppers on the active layer. The oxide semiconductor layer may be a ternary system or quaternary system oxide semiconductor comprising a combination of AxByCzO (A, B, C=Zn, Cd, Ga, In, Sn, Hf, Zr; x, y, z≧0).

摘要翻译： 一种制造氧化物薄膜晶体管的方法，包括顺序地形成栅极绝缘膜，氧化物半导体层和第一绝缘层; 选择性地图案化氧化物半导体层和第一绝缘层以在栅电极上形成有源层和绝缘层图案; 在其上形成有活性层和绝缘层图案的基板上形成第二绝缘层; 以及选择性地图案化所述绝缘层图案和所述第二绝缘层以在所述有源层上形成第一和第二蚀刻阻挡层。 氧化物半导体层可以是包含AxByCzO（A，B，C = Zn，Cd，Ga，In，Sn，Hf，Zr; x，y，z≥0）的组合的三元系或四元系氧化物半导体。

公开(公告)号：US06640112B1

公开(公告)日：2003-10-28

申请号：US09696320

申请日：2000-10-25

申请人： Jin-Woo Lee ,  Byung-Kook Choi ,  Jong-Ok Kim ,  Jung-Hwan Byun ,  Chang-Yun Kim

发明人： Jin-Woo Lee ,  Byung-Kook Choi ,  Jong-Ok Kim ,  Jung-Hwan Byun ,  Chang-Yun Kim

IPC分类号： H04B138

CPC分类号： H04B7/0671 ,  H04B7/15

摘要： A repeating method for a wireless communication system which provides time and space diversities, and an apparatus thereof are disclosed. The method of repeating a forward link communication signal for a wireless communication system includes the steps of: a) transmitting the forward link communication signal through a first transmitting antenna; b) delaying the forward link communication signal for a predetermined time period; and c) transmitting a delayed forward link communication signal which is generated by step b) through a second transmitting antenna. According to the method, when repeating forward and reverse link communication signals, time and space diversities are respectively provided to the base station and the mobile stations.

摘要翻译： 公开了一种提供时间和空间多样性的无线通信系统的重复方法及其装置。 重复无线通信系统的前向链路通信信号的方法包括以下步骤：a）通过第一发射天线发送前向链路通信信号; b）将所述前向链路通信信号延迟预定时间段; 以及c）通过第二发送天线发送由步骤b）生成的延迟前向链路通信信号。 根据该方法，当重复前向和反向链路通信信号时，分别向基站和移动台提供时间和空间多样性。

公开(公告)号：US07528409B2

公开(公告)日：2009-05-05

申请号：US11639567

申请日：2006-12-15

申请人： Hyo-Uk Kim ,  Chang-Bin Lee ,  Byung-Kook Choi ,  Dong-Young Kim

发明人： Hyo-Uk Kim ,  Chang-Bin Lee ,  Byung-Kook Choi ,  Dong-Young Kim

IPC分类号： H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/04 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/15 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F2001/136236 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/78633

摘要： An array substrate for a liquid crystal display device includes a substrate, a gate line on the substrate, a data line crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line and including a gate electrode, an active layer, an ohmic contact layer, a buffer metallic layer, a source electrode and a drain electrode, and a pixel electrode in the pixel region and connected to the thin film transistor, wherein the data line includes a transparent conductive layer and an opaque conductive layer, and each of the source and drain electrodes and the pixel electrode includes a transparent conductive layer.

摘要翻译： 用于液晶显示装置的阵列基板包括：基板，基板上的栅极线，与栅极线交叉以限定像素区域的数据线，连接到栅极线和数据线的薄膜晶体管，并且包括栅极 电极，有源层，欧姆接触层，缓冲金属层，源电极和漏电极，以及像素区域中的像素电极，并连接到薄膜晶体管，其中数据线包括透明导电层和 不透明导电层，源极和漏极以及像素电极中的每一个包括透明导电层。

公开(公告)号：US08687158B2

公开(公告)日：2014-04-01

申请号：US11818319

申请日：2007-06-14

申请人： Byung-Kook Choi ,  Hyo-Uk Kim ,  Chang-Bin Lee

发明人： Byung-Kook Choi ,  Hyo-Uk Kim ,  Chang-Bin Lee

IPC分类号： G02F1/1345

CPC分类号： H01L27/1288 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/1368 ,  H01L27/124 ,  H01L29/41733

摘要： An array substrate for an in-plane switching mode liquid crystal display device includes: a gate line on a substrate; a data line crossing the gate line to define a pixel region on the substrate; a common line parallel to and spaced apart from the gate line; a gate electrode connected to the gate line; a semiconductor layer disposed over the gate electrode, wherein an area of the semiconductor layer is less than an area of the gate electrode; a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode, the source and drain electrodes disposed on the semiconductor layer; a plurality of pixel electrodes integrated with the drain electrode and extending from the drain electrode in the pixel region; and a plurality of common electrodes connected to the common line and alternately arranged with the plurality of pixel electrodes, wherein each of the source electrode, the drain electrode, the data line and the plurality of pixel electrodes are comprised from a first conductive material layer and a second conductive material layer, wherein the second conductive material layer is disposed on the first conductive material layer.

摘要翻译： 面内切换模式液晶显示装置的阵列基板包括：基板上的栅极线; 跨越所述栅极线以限定所述衬底上的像素区域的数据线; 与栅极线平行并间隔开的公共线; 连接到栅极线的栅电极; 设置在所述栅电极上的半导体层，其中所述半导体层的面积小于所述栅电极的面积; 连接到数据线的源电极和与源电极间隔开的漏电极，设置在半导体层上的源电极和漏电极; 多个像素电极，与漏电极集成并在像素区域中从漏电极延伸; 以及连接到所述公共线并与所述多个像素电极交替布置的多个公共电极，其中所述源电极，所述漏电极，所述数据线和所述多个像素电极中的每一个包括第一导电材料层和 第二导电材料层，其中所述第二导电材料层设置在所述第一导电材料层上。

公开(公告)号：US20100273284A1

公开(公告)日：2010-10-28

申请号：US12831328

申请日：2010-07-07

申请人： Chang-Bin LEE ,  Byung-Kook Choi

发明人： Chang-Bin LEE ,  Byung-Kook Choi

IPC分类号： H01L21/336

CPC分类号： G02F1/1362 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/136231 ,  G02F2201/123

摘要： A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate electrode and a gate line on a substrate through a first mask process, forming a first insulating layer, an active layer, an ohmic contact layer, a buffer metallic layer, and a data line on the substrate including the gate electrode and the gate line through a second mask process, and forming a source electrode, a drain electrode, and a pixel electrode through a third mask process, the pixel electrode extending from the drain electrode, wherein the active layer is disposed over and within the gate electrode.

摘要翻译： 一种制造液晶显示装置用阵列基板的方法包括通过第一掩模工艺在基板上形成栅电极和栅极线，形成第一绝缘层，有源层，欧姆接触层，缓冲金属层 以及通过第二掩模处理在包括栅电极和栅极线的基板上的数据线，并且通过第三掩模处理形成源电极，漏电极和像素电极，从漏电极延伸的像素电极 ，其中所述有源层设置在所述栅电极之上和之内。

公开(公告)号：US07768587B2

公开(公告)日：2010-08-03

申请号：US11638437

申请日：2006-12-14

申请人： Chang-Bin Lee ,  Byung-Kook Choi

发明人： Chang-Bin Lee ,  Byung-Kook Choi

IPC分类号： G02F1/136

CPC分类号： G02F1/1362 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/136231 ,  G02F2201/123

摘要： An array substrate for a liquid crystal display device includes a substrate, a gate line on the substrate, a data line crossing the gate line to define a pixel region, a thin film transistor including a gate electrode, an active layer, an ohmic contact layer, a buffer metallic layer, a source electrode and a drain electrode, the thin film transistor being electrically connected to the gate line and the data line and a pixel electrode in the pixel region and connected to the thin film transistor, wherein the active layer is disposed over and within the gate electrode.

摘要翻译： 液晶显示装置用阵列基板包括：基板，基板上的栅极线，与栅极线交叉以形成像素区域的数据线;薄膜晶体管，包括栅电极，有源层，欧姆接触层 缓冲金属层，源电极和漏电极，薄膜晶体管电连接到像素区域中的栅极线和数据线以及像素电极，并连接到薄膜晶体管，其中有源层是 设置在栅电极之上和之内。

公开(公告)号：US20080013026A1

公开(公告)日：2008-01-17

申请号：US11818319

申请日：2007-06-14

申请人： Byung-Kook Choi ,  Hyo-Uk Kim ,  Chang-Bin Lee

发明人： Byung-Kook Choi ,  Hyo-Uk Kim ,  Chang-Bin Lee

IPC分类号： G02F1/1343 ,  H01L21/82

CPC分类号： H01L27/1288 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/1368 ,  H01L27/124 ,  H01L29/41733

摘要： An array substrate for an in-plane switching mode liquid crystal display device includes: a gate line on a substrate; a data line crossing the gate line to define a pixel region on the substrate; a common line parallel to and spaced apart from the gate line; a gate electrode connected to the gate line; a semiconductor layer disposed over the gate electrode, wherein an area of the semiconductor layer is less than an area of the gate electrode; a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode, the source and drain electrodes disposed on the semiconductor layer; a plurality of pixel electrodes integrated with the drain electrode and extending from the drain electrode in the pixel region; and a plurality of common electrodes connected to the common line and alternately arranged with the plurality of pixel electrodes, wherein each of the source electrode, the drain electrode, the data line and the plurality of pixel electrodes are comprised from a first conductive material layer and a second conductive material layer, wherein the second conductive material layer is disposed on the first conductive material layer.

摘要翻译： 面内切换模式液晶显示装置的阵列基板包括：基板上的栅极线; 跨越所述栅极线以限定所述衬底上的像素区域的数据线; 与栅极线平行并间隔开的公共线; 连接到栅极线的栅电极; 设置在所述栅电极上的半导体层，其中所述半导体层的面积小于所述栅电极的面积; 连接到数据线的源电极和与源电极间隔开的漏电极，设置在半导体层上的源电极和漏电极; 多个像素电极，与漏电极集成并在像素区域中从漏电极延伸; 以及连接到所述公共线并与所述多个像素电极交替布置的多个公共电极，其中所述源电极，所述漏电极，所述数据线和所述多个像素电极中的每一个包括第一导电材料层和 第二导电材料层，其中所述第二导电材料层设置在所述第一导电材料层上。

公开(公告)号：US08243222B2

公开(公告)日：2012-08-14

申请号：US12831328

申请日：2010-07-07

申请人： Chang-Bin Lee ,  Byung-Kook Choi

发明人： Chang-Bin Lee ,  Byung-Kook Choi

IPC分类号： G02F1/136 ,  G02F1/1343

CPC分类号： G02F1/1362 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/136231 ,  G02F2201/123

摘要： A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate electrode and a gate line on a substrate through a first mask process, forming a first insulating layer, an active layer, an ohmic contact layer, a buffer metallic layer, and a data line on the substrate including the gate electrode and the gate line through a second mask process, and forming a source electrode, a drain electrode, and a pixel electrode through a third mask process, the pixel electrode extending from the drain electrode, wherein the active layer is disposed over and within the gate electrode.

摘要翻译： 一种制造液晶显示装置用阵列基板的方法包括通过第一掩模工艺在基板上形成栅电极和栅极线，形成第一绝缘层，有源层，欧姆接触层，缓冲金属层 以及通过第二掩模处理在包括栅电极和栅极线的基板上的数据线，并且通过第三掩模处理形成源电极，漏电极和像素电极，从漏电极延伸的像素电极 ，其中所述有源层设置在所述栅电极之上和之内。

公开(公告)号：US08198111B2

公开(公告)日：2012-06-12

申请号：US12410839

申请日：2009-03-25

申请人： Hyo-Uk Kim ,  Chang-Bin Lee ,  Byung-Kook Choi ,  Dong-Young Kim

发明人： Hyo-Uk Kim ,  Chang-Bin Lee ,  Byung-Kook Choi ,  Dong-Young Kim

IPC分类号： H01L21/308 ,  H01L33/00

CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F2001/136236 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/78633

摘要： An array substrate for a liquid crystal display device includes a substrate, a gate line on the substrate, a data line crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line and including a gate electrode, an active layer, an ohmic contact layer, a buffer metallic layer, a source electrode and a drain electrode, and a pixel electrode in the pixel region and connected to the thin film transistor, wherein the data line includes a transparent conductive layer and an opaque conductive layer, and each of the source and drain electrodes and the pixel electrode includes a transparent conductive layer.

摘要翻译： 用于液晶显示装置的阵列基板包括：基板，基板上的栅极线，与栅极线交叉以限定像素区域的数据线，连接到栅极线和数据线的薄膜晶体管，并且包括栅极 电极，有源层，欧姆接触层，缓冲金属层，源电极和漏电极，以及像素区域中的像素电极，并连接到薄膜晶体管，其中数据线包括透明导电层和 不透明导电层，源极和漏极以及像素电极中的每一个包括透明导电层。