公开(公告)号：US20130083597A1

公开(公告)日：2013-04-04

申请号：US13423610

申请日：2012-03-19

申请人： Dai NAKAMURA ,  Koji Hosono ,  Hidehiro Shiga

发明人： Dai NAKAMURA ,  Koji Hosono ,  Hidehiro Shiga

IPC分类号： G11C16/28 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/16 ,  G11C16/28

摘要： According to one embodiment, a semiconductor memory device includes first and second select transistors, memory cells, a driver circuit, first transfer transistors, and a detection circuit. The memory cells are stacked above a semiconductor substrate. The driver circuit outputs a first voltage. The first transfer transistors transfer the first voltage to associated word lines and select gate lines. In data erase, the detection circuit detects a second voltage applied to bit lines and/or a source line and generates a flag in accordance with the detection result. The driver circuit changes the value of the first voltage in response to the flag to cut off the first transfer transistors.

摘要翻译： 根据一个实施例，半导体存储器件包括第一和第二选择晶体管，存储单元，驱动电路，第一传输晶体管和检测电路。 存储单元堆叠在半导体衬底之上。 驱动电路输出第一电压。 第一传输晶体管将第一电压转移到相关联的字线并选择栅极线。 在数据擦除中，检测电路检测施加到位线和/或源极线的第二电压，并根据检测结果生成标志。 驱动电路响应于标志来改变第一电压的值以切断第一转移晶体管。

公开(公告)号：US08724391B2

公开(公告)日：2014-05-13

申请号：US13423610

申请日：2012-03-19

申请人： Dai Nakamura ,  Koji Hosono ,  Hidehiro Shiga

发明人： Dai Nakamura ,  Koji Hosono ,  Hidehiro Shiga

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/16 ,  G11C16/28

摘要： According to one embodiment, a semiconductor memory device includes first and second select transistors, memory cells, a driver circuit, first transfer transistors, and a detection circuit. The memory cells are stacked above a semiconductor substrate. The driver circuit outputs a first voltage. The first transfer transistors transfer the first voltage to associated word lines and select gate lines. In data erase, the detection circuit detects a second voltage applied to bit lines and/or a source line and generates a flag in accordance with the detection result. The driver circuit changes the value of the first voltage in response to the flag to cut off the first transfer transistors.

摘要翻译： 根据一个实施例，半导体存储器件包括第一和第二选择晶体管，存储单元，驱动电路，第一传输晶体管和检测电路。 存储单元堆叠在半导体衬底之上。 驱动电路输出第一电压。 第一传输晶体管将第一电压转移到相关联的字线并选择栅极线。 在数据擦除中，检测电路检测施加到位线和/或源极线的第二电压，并根据检测结果生成标志。 驱动电路响应于标志来改变第一电压的值以切断第一转移晶体管。

公开(公告)号：US08274846B2

公开(公告)日：2012-09-25

申请号：US12652612

申请日：2010-01-05

申请人： Hidehiro Shiga ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Daisaburo Takashima

IPC分类号： G11C5/14

CPC分类号： G11C7/14 ,  G11C5/147 ,  G11C11/22

摘要： A reference voltage generation circuit includes a first node settable at a reference voltage to be any one of a plurality of voltage levels, a second node set at a pre-charge voltage, first and second switches connected in series between the first and second nodes, a plurality of capacitors, each capacitor comprising a first end connected to a connection node between the first and second switches and a second end settable at an independent voltage level, a switch controller configured to turn off the first switch and turn on the second switch in an initial state, and then to turn off the second switch, and then to turn on the first switch, and a voltage controller configured to individually set a voltage at the second end of each capacitor after the first switch is turned on.

摘要翻译： 参考电压产生电路包括可设置为参考电压的第一节点，其为多个电压电平中的任何一个，在预充电电压下设置的第二节点，串联连接在第一和第二节点之间的第一和第二开关， 多个电容器，每个电容器包括连接到第一和第二开关之间的连接节点的第一端和可设置在独立电压电平的第二端;开关控制器，被配置为关闭第一开关并将第二开关导通 初始状态，然后关闭第二开关，然后打开第一开关，并且电压控制器被配置为在第一开关导通之后单独设置每个电容器的第二端处的电压。

公开(公告)号：US20110044087A1

公开(公告)日：2011-02-24

申请号：US12684375

申请日：2010-01-08

申请人： Hidehiro Shiga ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Daisaburo Takashima

IPC分类号： G11C11/22 ,  G11C7/06

CPC分类号： G11C11/22

摘要： A memory includes ferroelectric capacitors; sense amplifiers configured to detect the data stored in ferroelectric capacitors; and a plate control circuit configured to receive a plate driving signal driving a plate line, a write signal indicating writing of data from an outside to the sense amplifier, and an operation end signal indicating end of an executable period for reading or writing data between the sense amplifier and the outside, the plate control circuit validating or invalidating the plate driving signal based on the write signal and the operation end signal wherein the plate control circuit validates the plate driving signal in the executable period, and the plate control circuit invalidates the plate driving signal at the end of the executable period when the write signal is never activated in the executable period, and keeps the plate driving signal valid when the write signal is activated in the executable period.

摘要翻译： 存储器包括铁电电容器; 感测放大器，被配置为检测存储在铁电电容器中的数据; 以及板控制电路，被配置为接收驱动板线的板驱动信号，指示从外部向读出放大器写入数据的写入信号，以及指示可执行周期结束的操作结束信号，用于在 读出放大器和外部，板控制电路基于写入信号和操作结束信号来验证或使板驱动信号无效，其中板控制电路在可执行周期中验证板驱动信号，并且板控制电路使板 在可执行期间写入信号从不被激活的可执行期间结束时的驱动信号，并且在可执行期间写入信号被激活时，保持板驱动信号有效。

公开(公告)号：US07385836B2

公开(公告)日：2008-06-10

申请号：US11265188

申请日：2005-11-03

申请人： Hidehiro Shiga ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A reference bit line which supplies a reference potential to a sense amplifier circuit is connected to the sense amplifier circuit. A reference potential generating circuit is connected to the reference bit line. The reference potential generating circuit includes a selection transistor which is connected at one end to the reference bit line, and a paraelectric capacitor connected between the other end of the selection transistor and a dummy plate line. A dummy plate line driver is connected to the dummy plate line. The dummy plate line driver drives the dummy plate line to a first voltage which is higher than an operating voltage of the sense amplifier circuit, when the reference potential generating circuit generates the reference potential.

摘要翻译： 向读出放大器电路提供参考电位的参考位线连接到读出放大器电路。 参考电位产生电路连接到参考位线。 参考电位产生电路包括一端连接到参考位线的选择晶体管和连接在选择晶体管的另一端和虚设板线之间的顺电电容器。 虚拟板线驱动器连接到虚拟板线。 当参考电位产生电路产生参考电位时，虚拟板线驱动器将虚拟板线驱动到高于读出放大器电路的工作电压的第一电压。

公开(公告)号：US20080068874A1

公开(公告)日：2008-03-20

申请号：US11898605

申请日：2007-09-13

申请人： Hidehiro Shiga ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： This disclosure concerns a semiconductor memory device including a ferroelectric capacitor; a cell transistor having a source connected to a first electrode of the ferroelectric capacitor; bit lines; word lines; n plate lines corresponding to n column blocks and connected to a second electrodes of the ferroelectric capacitors in the corresponding column blocks, respectively, the n column blocks being obtained by dividing the cell array into the n column blocks for every set of m columns, where n≧2 and m≧2; a plurality of reset transistors connected between the bit lines and the n plate lines; and m reset lines corresponding to the m columns within the column blocks and connected to gates of n reset transistors of the reset transistors, the n reset transistors being respectively provided in n columns respectively included in the n column blocks.

摘要翻译： 本公开涉及包括铁电电容器的半导体存储器件; 电池晶体管，其源极连接到所述铁电电容器的第一电极; 位线 字线 n列板对应于n列块，分别连接到相应列块中的铁电电容器的第二电极，n列块是通过将每个m列的单元阵列划分成n列块而获得的，其中 n> = 2且m> = 2; 多个复位晶体管，连接在所述位线与所述n条线之间; 和m个复位线，其对应于列块内的m列，并连接到复位晶体管的n个复位晶体管的栅极，n个复位晶体管分别设置在分别包含在n个列块中的n列中。

公开(公告)号：US07315194B2

公开(公告)日：2008-01-01

申请号：US10923717

申请日：2004-08-24

申请人： Hidehiro Shiga ,  Shinichiro Shiratake ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Shinichiro Shiratake ,  Daisaburo Takashima

IPC分类号： G05F1/10

CPC分类号： H02M3/073 ,  H02M2001/0041 ,  H02M2003/077

摘要： A booster circuit includes a first booster unit having a first output terminal from which a boosted voltage is output. The first output terminal is connected to an external output terminal. A second booster unit has a second output terminal from which a boosted voltage is output. The second output terminal is connected to the external output terminal. A control circuit outputs a first control signal used to control the operation of the first booster unit and a second control signal used to control the operation of the second booster unit. Further, the control circuit controls the first and second control signals so that a transition between the operative state and the non-operative state of the first booster unit and a transition between the operative state and the non-operative state of the second booster unit will be made at different timings according to output voltage of the external output terminal.

摘要翻译： 升压电路包括具有输出升压电压的第一输出端的第一升压单元。 第一个输出端子连接到外部输出端子。 第二升压单元具有输出升压电压的第二输出端子。 第二个输出端子连接到外部输出端子。 控制电路输出用于控制第一升压单元的运行的第一控制信号和用于控制第二升压单元的运行的第二控制信号。 此外，控制电路控制第一和第二控制信号，使得第一升压单元的操作状态和非操作状态之间的转变以及第二增压单元的操作状态和非操作状态之间的转变将 根据外部输出端子的输出电压在不同的定时进行。

公开(公告)号：US07561459B2

公开(公告)日：2009-07-14

申请号：US11898605

申请日：2007-09-13

申请人： Hidehiro Shiga ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： This disclosure concerns a semiconductor memory device including a ferroelectric capacitor; a cell transistor having a source connected to a first electrode of the ferroelectric capacitor; bit lines; word lines; n plate lines corresponding to n column blocks and connected to a second electrodes of the ferroelectric capacitors in the corresponding column blocks, respectively, the n column blocks being obtained by dividing the cell array into the n column blocks for every set of m columns, where n≧2 and m≧2; a plurality of reset transistors connected between the bit lines and the n plate lines; and m reset lines corresponding to the m columns within the column blocks and connected to gates of n reset transistors of the reset transistors, the n reset transistors being respectively provided in n columns respectively included in the n column blocks.

摘要翻译： 本公开涉及包括铁电电容器的半导体存储器件; 电池晶体管，其源极连接到所述铁电电容器的第一电极; 位线 字线 n列板对应于n列块，分别连接到相应列块中的铁电电容器的第二电极，n列块是通过将每个m列的单元阵列划分成n列块而获得的，其中 n> = 2且m> = 2; 多个复位晶体管，连接在所述位线与所述n条线之间; 和m个复位线，其对应于列块内的m列，并连接到复位晶体管的n个复位晶体管的栅极，n个复位晶体管分别设置在分别包含在n个列块中的n列中。

公开(公告)号：US07518901B2

公开(公告)日：2009-04-14

申请号：US11877890

申请日：2007-10-24

申请人： Hidehiro Shiga ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Daisaburo Takashima

IPC分类号： G11C11/22 ,  G11C11/24

CPC分类号： G11C11/22

摘要： A first ferroelectric memory cell and a second ferroelectric memory cell each include a ferroelectric capacitor and a transistor and each store one set of information. A word-line is shared by the first and second ferroelectric memory cells. A first plate line is connected to the first ferroelectric memory cell and a second plate line is connected to the second ferroelectric memory cell. A selection transistor has one end connected to the first and second ferroelectric memory cells and the other end connected to a bit-line.

摘要翻译： 第一铁电存储器单元和第二铁电存储单元各自包括铁电电容器和晶体管，并且每个存储一组信息。 字线由第一和第二铁电存储器单元共享。 第一板线连接到第一铁电存储单元，第二板线连接到第二铁电存储单元。 选择晶体管的一端连接到第一和第二铁电存储单元，另一端连接到位线。

公开(公告)号：US20070047288A1

公开(公告)日：2007-03-01

申请号：US11265188

申请日：2005-11-03

申请人： Hidehiro Shiga ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A reference bit line which supplies a reference potential to a sense amplifier circuit is connected to the sense amplifier circuit. A reference potential generating circuit is connected to the reference bit line. The reference potential generating circuit includes a selection transistor which is connected at one end to the reference bit line, and a paraelectric capacitor connected between the other end of the selection transistor and a dummy plate line. A dummy plate line driver is connected to the dummy plate line. The dummy plate line driver drives the dummy plate line to a first voltage which is higher than an operating voltage of the sense amplifier circuit, when the reference potential generating circuit generates the reference potential.

摘要翻译： 向读出放大器电路提供参考电位的参考位线连接到读出放大器电路。 参考电位产生电路连接到参考位线。 参考电位产生电路包括一端连接到参考位线的选择晶体管和连接在选择晶体管的另一端和虚设板线之间的顺电电容器。 虚拟板线驱动器连接到虚拟板线。 当参考电位产生电路产生参考电位时，虚拟板线驱动器将虚拟板线驱动到高于读出放大器电路的工作电压的第一电压。