公开(公告)号：US20130083597A1

公开(公告)日：2013-04-04

申请号：US13423610

申请日：2012-03-19

申请人： Dai NAKAMURA ,  Koji Hosono ,  Hidehiro Shiga

发明人： Dai NAKAMURA ,  Koji Hosono ,  Hidehiro Shiga

IPC分类号： G11C16/28 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/16 ,  G11C16/28

摘要： According to one embodiment, a semiconductor memory device includes first and second select transistors, memory cells, a driver circuit, first transfer transistors, and a detection circuit. The memory cells are stacked above a semiconductor substrate. The driver circuit outputs a first voltage. The first transfer transistors transfer the first voltage to associated word lines and select gate lines. In data erase, the detection circuit detects a second voltage applied to bit lines and/or a source line and generates a flag in accordance with the detection result. The driver circuit changes the value of the first voltage in response to the flag to cut off the first transfer transistors.

摘要翻译： 根据一个实施例，半导体存储器件包括第一和第二选择晶体管，存储单元，驱动电路，第一传输晶体管和检测电路。 存储单元堆叠在半导体衬底之上。 驱动电路输出第一电压。 第一传输晶体管将第一电压转移到相关联的字线并选择栅极线。 在数据擦除中，检测电路检测施加到位线和/或源极线的第二电压，并根据检测结果生成标志。 驱动电路响应于标志来改变第一电压的值以切断第一转移晶体管。

公开(公告)号：US20080094900A1

公开(公告)日：2008-04-24

申请号：US11874458

申请日：2007-10-18

申请人： Dai NAKAMURA ,  Koji Hosono

发明人： Dai NAKAMURA ,  Koji Hosono

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A nonvolatile semiconductor memory according to an example of the present invention includes first and second word lines extending in a first direction and having the same row address, a first block including the first word line and having a first block address, a second block including the second word line and having a second block address, first and second signal lines extending in a second direction crossing the first direction, a first transfer transistor connected between the first word line and the first signal line, a second transfer transistor connected between the second word line and the second signal line, and a transfer voltage selector to output a transfer voltage to the first and second signal lines.

摘要翻译： 根据本发明的示例的非易失性半导体存储器包括在第一方向上延伸并且具有相同行地址的第一和第二字线，包括第一字线并具有第一块地址的第一块，包括第二块的第二块 第二字线并且具有第二块地址，在与第一方向交叉的第二方向上延伸的第一和第二信号线，连接在第一字线和第一信号线之间的第一传输晶体管，连接在第二字之间的第二传输晶体管 线路和第二信号线，以及转移电压选择器，用于向第一和第二信号线输出转移电压。

公开(公告)号：US20080137409A1

公开(公告)日：2008-06-12

申请号：US11944803

申请日：2007-11-26

申请人： Dai NAKAMURA ,  Koji Hosono

发明人： Dai NAKAMURA ,  Koji Hosono

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344

摘要： A semiconductor memory device including a memory cell array with NAND cell units arranged therein, the NAND cell unit having a plurality of electrically rewritable and non-volatile memory cells connected in series, first and second select gate transistors disposed for coupling the both ends of the NAND cell unit to a bit line and a source line, respectively, and a dummy cell disposed adjacent to at least one of the first and second select gate transistors, wherein after erasing the memory cells in an erase unit, the memory cells excepting the dummy cell are subject to soft-program.

摘要翻译： 一种半导体存储器件，包括其中布置有NAND单元单元的存储单元阵列，所述NAND单元单元具有串联连接的多个电可重写和非易失性存储单元，第一和第二选择栅极晶体管被设置用于将 NAND单元分别连接到位线和源极线，以及与第一和第二选择栅晶体管中的至少一个相邻设置的虚设单元，其中在擦除单元中的存储单元擦除之后，除虚拟 单元格需要软件程序。

公开(公告)号：US20120243338A1

公开(公告)日：2012-09-27

申请号：US13425621

申请日：2012-03-21

申请人： Dai NAKAMURA

发明人： Dai NAKAMURA

IPC分类号： G11C16/04

CPC分类号： G11C16/16

摘要： A nonvolatile semiconductor storage device of an embodiment includes: a cell array including a plurality of memory cells formed on a well and configured by a charge accumulating layer and a control gate; a plurality of control gate lines that are paths for supplying a voltage necessary to access the memory cells to the control gates of the memory cells; and an erasing circuit that performs an erasing operation configured by an erasing period during which data of the memory cells are erased and a resetting period during which a post processing of the erasing period is performed, the erasing circuit applying an erasing voltage necessary to erase the data to the well of the memory cells during the erasing period, and discharging the erasing voltage applied to the well of the memory cells to a ground line via the control gate lines during the resetting period.

摘要翻译： 一个实施例的非易失性半导体存储装置包括：单元阵列，包括形成在阱上并由电荷累积层和控制栅极构成的多个存储单元; 多个控制栅极线，其是用于向存储器单元的控制栅极提供将存储单元访问所必需的电压的路径; 以及擦除电路，其执行擦除操作，所述擦除操作由擦除期间擦除存储器单元的数据，以及执行擦除周期的后处理的复位周期，所述擦除电路施加擦除所述擦除周期所需的擦除电压 在擦除期间向存储单元的阱提供数据，并且在复位周期期间通过控制栅极线将施加到存储单元的阱的擦除电压放电到接地线。

公开(公告)号：US20100277977A1

公开(公告)日：2010-11-04

申请号：US12727426

申请日：2010-03-19

申请人： Dai NAKAMURA

发明人： Dai NAKAMURA

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/16

摘要： A NAND flash memory includes a semiconductor substrate, a well region in the semiconductor substrate, memory cells connected in series in the well region, a discharge circuit connected to the well region, a word line connected to the memory cells, and a control circuit which controls potentials of the well region and the word line. The control circuit set the well region to a first potential, and set the word line to a second potential lower than the first potential, in an erase operation. The discharge circuit comprises a constant current source with a constant discharge speed independent on a temperature, and discharges the well region after the erase operation.

摘要翻译： NAND闪存包括半导体衬底，半导体衬底中的阱区，在阱区中串联连接的存储单元，连接到阱区的放电电路，连接到存储单元的字线和控制电路， 控制井区和字线的电位。 在擦除操作中，控制电路将阱区域设置为第一电位，并将字线设置为低于第一电位的第二电位。 放电电路包括恒定的恒定电流源，其恒定的放电速度与温度无关，并且在擦除操作之后对阱区域进行放电。

公开(公告)号：US20100176422A1

公开(公告)日：2010-07-15

申请号：US12649822

申请日：2009-12-30

申请人： Koichi FUKUDA ,  Dai NAKAMURA ,  Yasuhiko MATSUNAGA

发明人： Koichi FUKUDA ,  Dai NAKAMURA ,  Yasuhiko MATSUNAGA

IPC分类号： H01L27/10 ,  H01L21/82

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a semiconductor substrate; a memory cell array on the semiconductor substrate, the memory cell array comprising a plurality of memory cells capable of electrically storing data; a sense amplifier configured to detect the data stored in at least one of the memory cells; a cell source driver electrically connected to source side terminals of the memory cells and configured to supply a source potential to at least one of the source side terminals of the memory cells; a first wiring configured to electrically connect between at least one of the source side terminals of the memory cells and the cell source driver; and a second wiring formed in a same wiring layer as the first wiring, the second wiring being insulated from the first wiring and being electrically connected to the sense amplifier, wherein the first wiring and the second wiring have a plurality of through holes provided at a predetermined interval.

摘要翻译： 半导体存储器件包括半导体衬底; 所述存储单元阵列包括能够电存储数据的多个存储单元;存储单元阵列， 感测放大器，被配置为检测存储在所述存储器单元中的至少一个中的数据; 电池源驱动器，电连接到存储器单元的源极端子，并且被配置为向存储器单元的至少一个源极侧端子提供源极电位; 第一布线，被配置为电连接所述存储单元的至少一个源极端子和所述单元源驱动器; 以及形成在与所述第一布线相同的布线层中的第二布线，所述第二布线与所述第一布线绝缘并且电连接到所述读出放大器，其中所述第一布线和所述第二布线具有设置在所述第一布线的多个通孔 预定间隔。

公开(公告)号：US20100165733A1

公开(公告)日：2010-07-01

申请号：US12646551

申请日：2009-12-23

申请人： Dai NAKAMURA ,  Koichi FUKUDA ,  Yoshihisa WATANABE ,  Makoto IWAI

发明人： Dai NAKAMURA ,  Koichi FUKUDA ,  Yoshihisa WATANABE ,  Makoto IWAI

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： A NAND nonvolatile semiconductor memory includes a plurality of series-connected memory cells each includes a charge storage layer and control gate electrode, a plurality of word lines respectively connected to control gate electrodes of the memory cells, a first selection transistor connected between one end of the memory cells and a source line, a second selection transistor connected between the other end of the memory cells and a bit line, and a driver configured to control voltages applied to the word lines. The driver applies a first voltage to a first word line connected to a selected memory cell, and applies a cutoff voltage that cuts off a channel of a memory cell to second word lines of a number not less than three arranged side by side on the source line side with respect to the first word line during a write operation.

摘要翻译： NAND非易失性半导体存储器包括多个串联存储单元，每个存储单元包括电荷存储层和控制栅极电极，分别连接到存储单元的控制栅电极的多条字线，连接在存储单元的一端 存储单元和源极线，连接在存储单元的另一端和位线之间的第二选择晶体管和被配置为控制施加到字线的电压的驱动器。 驱动器对连接到所选择的存储单元的第一字线施加第一电压，并且将截止电压切断到存储单元的通道的截止电压到源于并排布置在源上的不少于三个的数量的第二字线 在写入操作期间相对于第一字线的线侧。

公开(公告)号：US20100067300A1

公开(公告)日：2010-03-18

申请号：US12537549

申请日：2009-08-07

申请人： Dai NAKAMURA

发明人： Dai NAKAMURA

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/16 ,  G11C16/0483

摘要： A nonvolatile semiconductor memory device includes: a memory cell array configured to have a plurality of blocks arranged thereon, each of the blocks being configured by an assembly of NAND cell units, each of the NAND cell units including a plurality of nonvolatile memory cells connected in series and word lines configured to commonly connect control gates of the memory cells. A data erase operation is executed by first applying a pre-charge voltage to the word lines, then setting to a floating state the word lines in a non-selected block where erasure of data is not to be executed, applying a certain voltage to the word lines in a selected block where erasure of data is to be executed and applying an erase voltage to a well where the memory cell array is formed, thereby altering a threshold voltage of the memory cells in the selected block.

摘要翻译： 非易失性半导体存储器件包括：存储单元阵列，被配置为具有布置在其上的多个块，每个块由NAND单元单元的组合构成，每个NAND单元单元包括多个非易失性存储单元， 串行和字线被配置为共同连接存储器单元的控制门。 执行数据擦除操作，首先对字线施加预充电电压，然后将浮动状态设置为不被执行擦除数据的未选择块中的字线，向 在要执行数据擦除的所选块中的字线，并且将擦除电压施加到形成存储单元阵列的阱中，由此改变所选块中的存储单元的阈值电压。

公开(公告)号：US20090303799A1

公开(公告)日：2009-12-10

申请号：US12409676

申请日：2009-03-24

申请人： Dai NAKAMURA

发明人： Dai NAKAMURA

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C5/02

CPC分类号： G11C16/344 ,  G11C16/16 ,  G11C16/3431

摘要： A non-volatile semiconductor memory device including a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, one end thereof being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein the memory device has an erase-verify mode for verifying an erase state of the memory cells in the NAND cell unit, the erase-verify mode including two verify-read operations adapted according to cell ranges to be erase-verified in the NAND cell unit.

摘要翻译： 一种非易失性半导体存储器件，包括具有串联连接的多个电可重写和非易失性存储单元的NAND单元单元，其一端经由第一选择栅极晶体管耦合到位线，而另一端耦合到 通过第二选择栅极晶体管的源极线，其中所述存储器件具有用于验证所述NAND单元单元中的存储器单元的擦除状态的擦除验证模式，所述擦除验证模式包括根据单元适应的两个验证读取操作 范围将在NAND单元单元中进行擦除验证。