公开(公告)号：US20070040619A1

公开(公告)日：2007-02-22

申请号：US11209117

申请日：2005-08-22

申请人： Dale McQuirk ,  Michael Berens

发明人： Dale McQuirk ,  Michael Berens

IPC分类号： H03B5/12 ,  H03L7/099

CPC分类号： H01L27/101 ,  H03B2201/0266 ,  H03J2200/10

摘要： A programmable capacitor array does not require separate switching transistors because the capacitors themselves have a switchable capacitance, which capacitors are made in the manner of regular N channel transistors with their source/drains connected to each other. When a logic low is applied to the gate, the capacitance is relatively low and the capacitance is what is commonly called parasitic capacitance. The capacitance increases significantly when a logic high is applied to the gate because the logic high has the effect of inverting the channel. Thus, the capacitor array is made of transistors that themselves have switchable capacitance operated so that no separate switching transistors are required. This allows for construction of an array of unit capacitors to achieve monotonic operation and good linearity using conventional manufacturing of N channel transistors while achieving significant area savings and reduced power consumption.

摘要翻译： 可编程电容器阵列不需要单独的开关晶体管，因为电容器本身具有可切换电容，这些电容器以其源极/漏极相互连接的常规N沟道晶体管的方式制成。 当逻辑低电平施加到栅极时，电容相对较低，电容通常称为寄生电容。 当逻辑高电平施加到栅极时，电容显着增加，因为逻辑高电平具有反相通道的作用。 因此，电容器阵列由其自身具有可切换电容操作的晶体管制成，使得不需要单独的开关晶体管。 这允许使用N沟道晶体管的常规制造来实现单元电容器阵列以实现单调操作和良好的线性度，同时实现显着的面积节省和降低的功耗。

公开(公告)号：US20070080740A1

公开(公告)日：2007-04-12

申请号：US11244515

申请日：2005-10-06

申请人： Michael Berens ,  James Feddeler ,  Dale McQuirk

发明人： Michael Berens ,  James Feddeler ,  Dale McQuirk

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： A reference circuit provides a reference voltage and a reference current that are both temperature and a power supply voltage independent. The reference circuit includes a bandgap reference circuit, a current source, and a resistor. The bandgap reference circuit provides a feedback voltage to control the current source and thereby generate a temperature independent voltage and a PTAT (proportional to absolute temperature) current. A resistor having a positive temperature coefficient is coupled to the feedback controlled current source to provide a CTAT (complementary to absolute temperature) current. The CTAT current is summed directly into the feedback controlled current source to produce a reference current that is substantially constant over a range of temperatures.

摘要翻译： 参考电路提供了温度和电源电压无关的参考电压和参考电流。 参考电路包括带隙参考电路，电流源和电阻器。 带隙参考电路提供反馈电压以控制电流源，从而产生与温度无关的电压和PTAT（与绝对温度成比例）的电流。 具有正温度系数的电阻器耦合到反馈控制电流源以提供CTAT（与绝对温度互补）电流。 CTAT电流直接与反馈控制的电流源相加，以产生在一定温度范围内基本恒定的参考电流。

公开(公告)号：US20070126480A1

公开(公告)日：2007-06-07

申请号：US11297191

申请日：2005-12-07

申请人： Dale McQuirk ,  Michael Bourland

发明人： Dale McQuirk ,  Michael Bourland

IPC分类号： H03K5/153

CPC分类号： H03K5/003 ,  H03K5/1532

摘要： A fully differential peak detection circuit includes programmable sensitivity and an autozero function. The peak detector has a fully differential charge-coupled analog signal path. The entire analog signal path is autozeroed upon enable and/or in response to sensing a logic zero at the output, where the logic zero follows a logic one. The peak detector includes a differential gain stage for receiving an analog input signal. The differential gain stage includes offset error compensation. The offset error compensation is selected upon enable and/or in response to an output signal of the peak detection circuit and automatically zeros an offset error voltage in response to a predetermined logic state of the output signal. The output of the gain stage is provided to a comparator stage. A plurality of capacitors coupled to the comparator stage stores a predetermined voltage for setting a sensitivity of the peak detector. The sensitivity is programmable during an autozero sequence by applying a predetermined voltage to the plurality of capacitors.

摘要翻译： 全差分峰值检测电路包括可编程灵敏度和自动归零功能。 峰值检测器具有完全差分的电荷耦合模拟信号路径。 在使能和/或响应于在输出处感测到逻辑零时，整个模拟信号路径被自动归零，其中逻辑0跟随逻辑1。 峰值检测器包括用于接收模拟输入信号的差分增益级。 差分增益级包括偏移误差补偿。 在使能和/或响应于峰值检测电路的输出信号时选择偏移误差补偿，并响应于输出信号的预定逻辑状态自动将偏移误差电压置零。 增益级的输出提供给比较器级。 耦合到比较器级的多个电容器存储用于设置峰值检测器的灵敏度的预定电压。 通过对多个电容器施加预定的电压，灵敏度可以在自动调零序列期间被编程。

公开(公告)号：US20070090848A1

公开(公告)日：2007-04-26

申请号：US11257706

申请日：2005-10-25

申请人： Kenneth Tumin ,  George Baker ,  Dale McQuirk ,  Matthew Stout

发明人： Kenneth Tumin ,  George Baker ,  Dale McQuirk ,  Matthew Stout

IPC分类号： G01R31/02

CPC分类号： G01R31/31704 ,  G01R31/3172

摘要： A design-for-test (DFT) circuit for an integrated circuit (IC) for enabling accurate quiescent current testing. The IC includes a voltage supply pin, a ground pin and an internal voltage regulator coupled between the voltage supply and ground pins for providing an internal output voltage. The DFT circuit includes a voltage storage device which couples to the voltage regulator to temporarily maintain the internal output voltage when the voltage regulator is disabled. The mode control circuit detects a quiescent current test mode, disables the voltage regulator and decouples the voltage regulator from the voltage storage device when the quiescent current test mode is detected. The DFT circuit may include an enable circuit which generates a freeze signal when the quiescent current test mode is detected, and at least one switch which decouples the voltage regulator from the voltage storage node. The DFT circuit is particularly useful for low pin-count ICs.