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公开(公告)号：US5570356A
公开(公告)日：1996-10-29
申请号：US486541
申请日：1995-06-07
CPC分类号： H04Q11/04
摘要： A data communication system includes a phase splitting circuit to split a high speed parallel data word into a number of individual parallel data bytes, a byte multiplexor for each of the phases of a phase splitting circuit, encoding and serialization circuits for converting each byte such as an 8-bit byte to an encoded form suitable for serial transmission such as by employing the Widmer et al. 8-bit/10-bit code, transmitting each encoded byte across one of a number of serial transmission links to a receiving device where the data is deserialized and decoded to recover the original byte which is then synchronized by a byte synchronization circuit. The byte synchronization circuits are then coupled to a word synchronization circuit where the original high bandwidth data word is recovered and transmitted on an internal high speed parallel bus within the receiving device.
摘要翻译： 数据通信系统包括：将高速并行数据字分割为若干个并行数据字节的相位分离电路，分相电路的每个相位的字节多路复用器，用于转换每个字节的编码和串行化电路， 一个8位字节到适合于串行传输的编码形式，例如通过使用Widmer等人 8位/ 10位代码，将多个串行传输链路之一的每个编码字节传送到数据被反序列化和解码的接收设备，以恢复原始字节，然后由字节同步电路同步。 字节同步电路然后被耦合到字同步电路，其中原始高带宽数据字被恢复并在接收设备内的内部高速并行总线上传输。
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公开(公告)号：US5487092A
公开(公告)日：1996-01-23
申请号：US363121
申请日：1994-12-22
CPC分类号： H04L7/02 , H04L7/0338 , H04L2007/045
摘要： A high-performance clock synchronizer for transferring digital data across the asynchronous boundary between two independent clock domains operating at hardware-limited clock speeds. The external clock signal latches each incoming data word in a boundary register. An external clock divider produces several prolonged clock signals synchronized to the external clock signal for use in distributing the incoming data words into a bank of several external buffer registers, where each word stabilizes for more than one full internal clock interval before transfer across the asynchronous boundary to a bank of corresponding internal buffer registers synchronized to the internal clock signal. A special logic inserts and deletes pad words to equalize data flow rates. Another special logic reassembles the data words in proper sequence after transfer to the internal buffer register bank. Flag latches are used to avoid asynchronous sampling of more than one bit in each data word.
摘要翻译： 一种高性能时钟同步器，用于在两个独立时钟域之间跨异步边界传输数字数据，这些时钟域以硬件限制的时钟速度运行。 外部时钟信号锁定边界寄存器中的每个输入数据字。 外部时钟分频器产生与外部时钟信号同步的多个延迟时钟信号，用于将输入的数据字分配到几个外部缓冲寄存器的组中，其中每个字在跨异步边界传输之前稳定多于一个完整的内部时钟间隔 到与内部时钟信号同步的相应内部缓冲寄存器组。 一个特殊的逻辑插入和删除pad字以均衡数据流速。 另一个特殊的逻辑在转移到内部缓冲寄存器组之后，以合适的顺序重新组合数据字。 标志锁存器用于避免每个数据字中多于一位的异步采样。
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