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公开(公告)号：US5487092A
公开(公告)日：1996-01-23
申请号：US363121
申请日：1994-12-22
CPC分类号： H04L7/02 , H04L7/0338 , H04L2007/045
摘要： A high-performance clock synchronizer for transferring digital data across the asynchronous boundary between two independent clock domains operating at hardware-limited clock speeds. The external clock signal latches each incoming data word in a boundary register. An external clock divider produces several prolonged clock signals synchronized to the external clock signal for use in distributing the incoming data words into a bank of several external buffer registers, where each word stabilizes for more than one full internal clock interval before transfer across the asynchronous boundary to a bank of corresponding internal buffer registers synchronized to the internal clock signal. A special logic inserts and deletes pad words to equalize data flow rates. Another special logic reassembles the data words in proper sequence after transfer to the internal buffer register bank. Flag latches are used to avoid asynchronous sampling of more than one bit in each data word.
摘要翻译： 一种高性能时钟同步器，用于在两个独立时钟域之间跨异步边界传输数字数据，这些时钟域以硬件限制的时钟速度运行。 外部时钟信号锁定边界寄存器中的每个输入数据字。 外部时钟分频器产生与外部时钟信号同步的多个延迟时钟信号，用于将输入的数据字分配到几个外部缓冲寄存器的组中，其中每个字在跨异步边界传输之前稳定多于一个完整的内部时钟间隔 到与内部时钟信号同步的相应内部缓冲寄存器组。 一个特殊的逻辑插入和删除pad字以均衡数据流速。 另一个特殊的逻辑在转移到内部缓冲寄存器组之后，以合适的顺序重新组合数据字。 标志锁存器用于避免每个数据字中多于一位的异步采样。
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公开(公告)号：US5570356A
公开(公告)日：1996-10-29
申请号：US486541
申请日：1995-06-07
CPC分类号： H04Q11/04
摘要： A data communication system includes a phase splitting circuit to split a high speed parallel data word into a number of individual parallel data bytes, a byte multiplexor for each of the phases of a phase splitting circuit, encoding and serialization circuits for converting each byte such as an 8-bit byte to an encoded form suitable for serial transmission such as by employing the Widmer et al. 8-bit/10-bit code, transmitting each encoded byte across one of a number of serial transmission links to a receiving device where the data is deserialized and decoded to recover the original byte which is then synchronized by a byte synchronization circuit. The byte synchronization circuits are then coupled to a word synchronization circuit where the original high bandwidth data word is recovered and transmitted on an internal high speed parallel bus within the receiving device.
摘要翻译： 数据通信系统包括：将高速并行数据字分割为若干个并行数据字节的相位分离电路，分相电路的每个相位的字节多路复用器，用于转换每个字节的编码和串行化电路， 一个8位字节到适合于串行传输的编码形式，例如通过使用Widmer等人 8位/ 10位代码，将多个串行传输链路之一的每个编码字节传送到数据被反序列化和解码的接收设备，以恢复原始字节，然后由字节同步电路同步。 字节同步电路然后被耦合到字同步电路，其中原始高带宽数据字被恢复并在接收设备内的内部高速并行总线上传输。
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公开(公告)号：US5630059A
公开(公告)日：1997-05-13
申请号：US383962
申请日：1995-02-06
申请人： James T. Brady , Damon W. Finney , David R. Nowlen
发明人： James T. Brady , Damon W. Finney , David R. Nowlen
CPC分类号： H04L49/9057 , G06F13/128 , H04L29/06 , H04L49/90 , H04L49/901 , H04L49/9052
摘要： A multi-nodal computing system is connected by a communication network. A first node of the multi-nodal system includes apparatus for transmitting an information transfer request to a second node, the request including identification data that the second node can use to access the selected information. The second node includes memory for storing the requested information and a message output control structure. A processor is responsive to received identification data from the first node to access selected information that is defined by the data. The processor is further responsive to the information transfer request to insert the identification data received from the first node directly into a message output control structure. The processor then initiates an output operation by employing the identification data in the message output control data structure to access the identified information and to communicate the information to the first node. In such manner, no processor interrupt is required (with software intervention) to enable the requested information to be transferred, as pointers to that information are already included in the message output control structure, with the output mechanism in the second node employing that output control structure to access and transmit the requested information.
摘要翻译： 多节点计算系统通过通信网络连接。 多节点系统的第一节点包括用于向第二节点发送信息传送请求的装置，所述请求包括第二节点可用于访问所选信息的标识数据。 第二节点包括用于存储所请求的信息和消息输出控制结构的存储器。 处理器响应于来自第一节点的接收到的标识数据来访问由数据定义的所选择的信息。 处理器进一步响应信息传送请求，将从第一节点接收的识别数据直接插入到消息输出控制结构中。 然后，处理器通过采用消息输出控制数据结构中的识别数据来发起输出操作来访问所识别的信息并将信息传送到第一节点。 以这种方式，由于在该消息输出控制结构中已经包括指向该信息的指针，所以不需要处理器中断（通过软件干预）来启用所请求的信息，其中第二节点中的输出机制使用该输出控制 结构来访问和传送所请求的信息。
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公开(公告)号：US5706443A
公开(公告)日：1998-01-06
申请号：US241904
申请日：1994-05-11
申请人： James T. Brady , Damon W. Finney , Michael H. Hartung , Donald J. Lang , Jaishankar M. Menon , David R. Nowlen , Calvin K. Tang
发明人： James T. Brady , Damon W. Finney , Michael H. Hartung , Donald J. Lang , Jaishankar M. Menon , David R. Nowlen , Calvin K. Tang
CPC分类号： G06F5/06
摘要： A system that enables pipelining of data to and from a memory includes multiple control block data structures which indicate amounts of data stored in the memory. An input port device receives and stores in memory, data segments of a received data message and only updates status information in the software control blocks when determined quantities of the data segments are stored. An output port is responsive to a request for transmission of a portion of the received data and to a signal from the input port that at least a first control count of data segments of the received data are present in memory. The output port then outputs the stored data segments from memory but discontinues the action if, before the required portion of the received data is outputted, software control blocks indicate that no further stored data segments are available for outputting. The input port then updates the software control blocks when newly arrived and stored data segments reach a second control count value, the updating occurring irrespective of whether the determined quantity of the received data has been stored in memory.
摘要翻译： 使得数据能够流向存储器和从存储器流出的系统包括指示存储在存储器中的数据量的多个控制块数据结构。 输入端口设备在存储器中接收并存储接收的数据消息的数据段，并且仅在存储确定的数据段的数量时才更新软件控制块中的状态信息。 输出端口响应于对接收到的数据的一部分的传输的请求和来自输入端口的信号，接收到的数据的数据段的至少第一控制计数存在于存储器中。 然后，输出端口从存储器输出存储的数据段，但是如果在输出所接收的数据的所需部分之前，软件控制块指示没有进一步存储的数据段可用于输出，则停止该动作。 然后，当新到达时，输入端口更新软件控制块，并且存储的数据段达到第二控制计数值，无论所确定的接收数据量是否已被存储在存储器中，更新发生。
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5.发明授权Multi-node network with internode switching performed within processor nodes, each node separately processing data and control messages 失效在节点间进行节点间切换的多节点网络，每个节点分别处理数据和控制消息
公开(公告)号：US5675736A
公开(公告)日：1997-10-07
申请号：US685770
申请日：1996-07-24
申请人： James Thomas Brady , Damon W. Finney , Michael Howard Hartung , Paul Wayne Hunter , Michael Anthony Ko , Donald J. Lang , Noah R. Mendelsohn , Jaishankar Moothedath Menon , David Ronald Nowlen
发明人： James Thomas Brady , Damon W. Finney , Michael Howard Hartung , Paul Wayne Hunter , Michael Anthony Ko , Donald J. Lang , Noah R. Mendelsohn , Jaishankar Moothedath Menon , David Ronald Nowlen
摘要： A distributed data processing system includes a plurality of nodes interconnected by bidirectional communication links. Each node includes a control message line for handling of control messages and a control memory for storing the control messages. Each node further includes data message line for handling of data messages and a data memory for storing the data messages. A processor in the node causes the data message line to queue and dispatch data messages from the data memory and the control message line to queue and dispatch control messages from the control memory. Each node includes N bidirectional communication links enabling the node to have at least twice as much input/output bandwidth as the control message line and data message line, combined. An input/output switch includes a routing processor and is coupled between the N bidirectional communication links, the data message line and control message line. The input/output switch dispatches either a control message or a data message over at least one of the bidirectional communication links in accordance with an output from the routing control processor, thereby enabling each communication link to carry either data or control messages. If a communication link is busy with either a control or a data message, the routing control processor increments to another communication link to enable dispatch of a queued message.
摘要翻译： 分布式数据处理系统包括通过双向通信链路互连的多个节点。 每个节点包括用于处理控制消息的控制消息线和用于存储控制消息的控制存储器。 每个节点还包括用于处理数据消息的数据消息行和用于存储数据消息的数据存储器。 节点中的处理器使得数据消息行从数据存储器和控制消息行排队和调度数据消息，以从控制存储器排队和调度控制消息。 每个节点包括N个双向通信链路，使得该节点具有至少两倍于控制消息行和数据消息行的输入/输出带宽。 输入/输出开关包括路由处理器，并且耦合在N个双向通信链路，数据消息线路和控制消息线路之间。 输入/输出交换机根据来自路由控制处理器的输出，通过至少一个双向通信链路分派控制消息或数据消息，从而使得每个通信链路能够携带数据或控制消息。 如果通信链路忙于控制或数据消息，则路由控制处理器递增到另一个通信链路以启用排队消息的分派。
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6.发明授权Adaptive and dynamic message routing system for multinode wormhole networks 失效用于多节点虫洞网络的自适应和动态消息路由系统
公开(公告)号：US5602839A
公开(公告)日：1997-02-11
申请号：US555539
申请日：1995-11-09
摘要： In a multinode communication or multiprocessor network, messages are communicated from one node to another using an adaptive and dynamic routing scheme. The routing scheme includes two-level multi-path routing tables at each node to ensure efficient delivery of the messages. An entry in the level-1 table identifies a group of nodes and entry in the level-2 table identifies the address for each node within that group. The routing scheme also includes a deflection counter in each message header to avoid endless rerouting of messages and an exponential backoff and retry policy to avoid deadlocks.
摘要翻译： 在多节点通信或多处理器网络中，使用自适应和动态路由方案将消息从一个节点传送到另一个节点。 路由方案包括每个节点的两层多路径路由表，以确保消息的有效传递。 level-1表中的一个条目标识一组节点，而level-2表中的条目标识该组中每个节点的地址。 路由方案还包括每个消息报头中的偏转计数器，以避免消息的无尽重新路由以及指数退避和重试策略以避免死锁。
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7.发明授权Dynamic memory allocation that enalbes efficient use of buffer pool memory segments 失效动态内存分配，有效利用缓冲池内存段
公开(公告)号：US5784698A
公开(公告)日：1998-07-21
申请号：US568180
申请日：1995-12-05
申请人： James Thomas Brady , Damon W. Finney , Michael Howard Hartung , Michael Anthony Ko , Noah R. Mendelsohn , Jaishankar Moothedath Menon , David R. Nowlen
发明人： James Thomas Brady , Damon W. Finney , Michael Howard Hartung , Michael Anthony Ko , Noah R. Mendelsohn , Jaishankar Moothedath Menon , David R. Nowlen
CPC分类号： G06F9/5016 , G06F12/023
摘要： An apparatus for dynamically allocating memory includes a processor, a free buffer pool memory and a control memory which stores control block data structures. The control block data structures enable a segmentation of the free buffer pool memory into a series of free buffer pools, each free buffer pool comprising plural identical size buffers, each succeeding free buffer pool including a larger buffer size than a preceding free buffer pool. A selection size parameter for a given free buffer pool is a value that is larger than the buffer size comprising the given free buffer pool, but less than a next larger buffer size in the next of the series of free buffer pools. A memory allocation procedure responds to a request from an executing procedure for allocation of buffer space by: (i) allocating a buffer from a free buffer pool memory whose associated selection size parameter is a next larger value than the buffer space that was requested; (ii) determining a difference between the allocated buffer size and the requested buffer space to find an unfulfilled amount of the requested buffer space; (iii) allocating a buffer from a free buffer pool memory whose selection size parameter is a next larger value, among selection size parameters, than the unfulfilled amount; and (iv) repeating ii and iii until the memory allocation procedure determines that there is no unfulfilled amount of the requested buffer space. The apparatus further includes "quickcell" memory which is allocated without use of control block data structures.
摘要翻译： 用于动态分配存储器的装置包括处理器，空闲缓冲池存储器和存储控制块数据结构的控制存储器。 控制块数据结构使得可以将空闲缓冲池存储器分割成一系列空闲缓冲池，每个空闲缓冲池包括多个相同大小的缓冲器，每个随后的空闲缓冲池包括比先前的空闲缓冲池大的缓冲器大小。 给定可用缓冲池的选择大小参数是大于包含给定可用缓冲池的缓冲区大小的值，但小于下一个空闲缓冲池系列中的下一个较大缓冲区大小的值。 存储器分配过程响应来自用于分配缓冲器空间的执行过程的请求，其通过以下步骤来响应：（i）从相关选择大小参数是比所请求的缓冲空间更大的值的空闲缓冲池存储器分配缓冲器; （ii）确定所分配的缓冲器大小与所请求的缓冲器空间之间的差异，以找到所请求的缓冲空间的未实现量; （iii）从选择大小参数中选择大小参数为选择大小参数的空闲缓冲池存储器中分配缓冲器，而不是未实现的量; 和（iv）重复ii和iii，直到存储器分配过程确定没有未实现的所请求的缓冲空间量。 该装置还包括在不使用控制块数据结构的情况下分配的“快速小区”存储器。
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公开(公告)号：US5712856A
公开(公告)日：1998-01-27
申请号：US749880
申请日：1996-11-15
IPC分类号： G06F11/22 , G06F13/00 , H04L12/26 , H04L29/06 , H04L29/14 , H04M3/22 , G01R31/28 , G06F11/00
CPC分类号： H04L43/50 , H04L12/2697 , H04L29/06 , H04L69/03
摘要： A test link protocol which continuously monitors each link in a network to ensure that the link is correctly transmitting data. Each switch, or torus has at least one of two functional components: Send Test and Receive Test. The Send Test component monitors control codes at a torus link output. The Receive Test component monitors control codes at a torus link input. After a predetermined interval, the Send Test component makes a request to send a test.sub.-- link control code. The torus sends the test.sub.-- link code to the neighboring torus, where it is removed from the data stream and sent to that torus' Receive Test. The Receive Test then generates a response message and makes a request to send that message back to the originating torus. After receiving the message, the Send Test analyzes the message to determine whether the network link is working correctly. An error is also declared if the Send Test does not receive a reply within a predetermined interval.
摘要翻译： 一种连续监视网络中每个链路以确保链路正确传输数据的测试链路协议。 每个开关或环面至少有两个功能组件之一：发送测试和接收测试。 发送测试组件监视环面链路输出端的控制代码。 接收测试组件监视环面连接输入端的控制代码。 在预定的时间间隔之后，发送测试组件请求发送测试链接控制代码。 环形天线将测试链接代码发送到相邻的环面，从数据流中删除并发送到该环面的“接收测试”。 接收测试然后生成一个响应消息，并发出请求将该消息发送回原始环面。 收到消息后，发送测试分析消息以确定网络链路是否正常工作。 如果发送测试没有在预定的时间间隔内收到回复，也会声明错误。
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9.发明授权System for controlling responses to requests over a data bus between a plurality of master controllers and a slave storage controller by inserting control characters 失效用于通过插入控制字符来控制在多个主控制器和从存储控制器之间的数据总线上对请求的响应的系统
公开(公告)号：US5687393A
公开(公告)日：1997-11-11
申请号：US480010
申请日：1995-06-07
CPC分类号： G06F13/161 , G06F13/1615
摘要： A data processing system includes one or more processors connected to a common bus, one or more I/O controllers connected to the common bus and to one or more storage subsystems and one or more storage subsystems for storing data for use in the data processing system. One or more master controllers are included in each I/O controller for communicating with a memory controller referred to as a slave which controls data flow to and from a memory subsystem. The data bus between the I/O masters and the memory controller is a multi-drop operating synchronously on a two-by-two byte parallel interface.
摘要翻译： 数据处理系统包括连接到公共总线的一个或多个处理器，连接到公共总线的一个或多个I / O控制器和一个或多个存储子系统以及用于存储用于数据处理系统的数据的一个或多个存储子系统 。 一个或多个主控制器被包括在每个I / O控制器中，用于与被称为从属的存储器控制器进行通信，所述存储器控制器控制到存储器子系统和从存储器子系统的数据流。 I / O主机和存储器控制器之间的数据总线是在两位二字节并行接口上同步进行多点操作。
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公开(公告)号：US5940612A
公开(公告)日：1999-08-17
申请号：US534585
申请日：1995-09-27
申请人： James Thomas Brady , Damon W. Finney , Michael Howard Hartung , Michael Anthony Ko , Noah R. Mendelsohn , Jaishankar Moothedath Menon , David R. Nowlen
发明人： James Thomas Brady , Damon W. Finney , Michael Howard Hartung , Michael Anthony Ko , Noah R. Mendelsohn , Jaishankar Moothedath Menon , David R. Nowlen
CPC分类号： G06F9/4881
摘要： A procedure controls execution of priority ordered tasks in a multi-nodel data processing system. The data processing system includes a node with a software-controlled processor and a hardware-configured queue-controller. The queue-controller includes a plurality of priority-ordered queues, each queue listing tasks having an assigned priority equal to a priority order assigned to the queue. The queue-controller responds to a processor generated order to queue a first task for execution, by performing a method which includes the steps of: listing said first task on a first queue having an assigned priority that is equal to a priority of said first task; if a second task is listed on a queue having a higher assigned priority, attempting execution of the second task before execution of the first task; if no tasks are listed on a queue having a higher assigned priority than said first queue, attempting execution of a first listed task in the first queue means; and upon completion of execution of the task or a stalling of execution of the task, attempting execution of a further task on the first queue only if another order has not been issued to place a task on a queue having a higher assigned priority. The method further handles chained subtasks by attempting execution of each subtask of a task in response to the processor generated order; and if execution of any subtask does not complete, attempting execution of another task in lieu of a subtask chained to the subtask that did not complete.
摘要翻译： 程序控制多节点数据处理系统中优先级排序任务的执行。 数据处理系统包括具有软件控制处理器和硬件配置的队列控制器的节点。 队列控制器包括多个优先级排序队列，每个队列列出具有分配给队列的优先顺序的分配优先级的任务。 队列控制器响应于处理器生成的顺序来排队第一任务以执行，方法是执行一种方法，该方法包括以下步骤：在具有等于所述第一任务的优先级的分配优先级的第一队列上列出所述第一任务 ; 如果在具有较高分配优先级的队列中列出第二任务，则在执行第一任务之前尝试执行第二任务; 如果在具有比所述第一队列更高的分配优先级的队列上列出任务，则尝试执行第一队列中的第一列出的任务; 并且在完成执行任务或停止执行任务时，只有当尚未发出另一个订单以将任务放置在具有较高分配优先级的队列上时，才尝试在第一队列上执行另外的任务。 该方法通过响应于处理器生成的顺序尝试执行任务的每个子任务来进一步处理链接子任务; 并且如果任何子任务的执行未完成，则尝试执行另一任务代替链接到未完成的子任务的子任务。
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