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1.发明申请DIGITAL PHASE-LOCKED LOOP WITH TWO-POINT MODULATION USING AN ACCUMULATOR AND A PHASE-TO-DIGITAL CONVERTER 有权使用累加器和相数转换器进行两点调制的数字锁相环公开(公告)号：US20100277211A1
公开(公告)日：2010-11-04
申请号：US12432468
申请日：2009-04-29
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03C3/0916 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L7/085
摘要： A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain.
摘要翻译： 描述了支持两点调制的数字锁相环（DPLL）。 在一种设计中，DPLL包括一个相位数转换器和一个环路工作的环路滤波器，一个用于低通调制路径的第一处理单元和一个用于高通调制路径的第二处理单元。 第一处理单元接收输入调制信号，并且在相位数转换器之后并且在环路滤波器之前向环路内的第一点提供第一调制信号。 第二处理单元接收输入调制信号，并且在环路滤波器之后向环路内的第二点提供第二调制信号。 第一处理单元可以包括累积输入调制信号以将频率转换为相位的累加器。 第二处理单元可以包括用可变增益来缩放输入调制信号的缩放单元。
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公开(公告)号：US08098103B2
公开(公告)日：2012-01-17
申请号：US12483927
申请日：2009-06-12
IPC分类号： H03L7/093
CPC分类号： H03L7/093
摘要： Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derived by analyzing one or more signals within the PLL. The signals within the PLL may be correlated against one or more disturbance signal templates, such as a sinusoid having a known frequency, to derive one or more correlation coefficients. The coefficients may be applied to weight one or more disturbance synthesis functions to generate the cancellation signal. Further aspects provide for joint analysis, synthesis, and cancellation of signals having unknown frequency from the PLL output.
摘要翻译： 从PLL输出信号中消除干扰信号的技术。 在一方面，消除信号与输入到PLL中的VCO或DCO的信号组合。 在另一方面，通过分析PLL内的一个或多个信号来导出适当的抵消信号。 PLL内的信号可以与一个或多个干扰信号模板（例如具有已知频率的正弦波）相关，以导出一个或多个相关系数。 可以应用系数来加权一个或多个干扰合成功能以产生消除信号。 其他方面提供了从PLL输出端对未知频率的信号的联合分析，合成和消除。
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公开(公告)号：US20100315169A1
公开(公告)日：2010-12-16
申请号：US12483927
申请日：2009-06-12
IPC分类号： H03L7/097
CPC分类号： H03L7/093
摘要： Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derived by analyzing one or more signals within the PLL. The signals within the PLL may be correlated against one or more disturbance signal templates, such as a sinusoid having a known frequency, to derive one or more correlation coefficients. The coefficients may be applied to weight one or more disturbance synthesis functions to generate the cancellation signal. Further aspects provide for joint analysis, synthesis, and cancellation of signals having unknown frequency from the PLL output.
摘要翻译： 从PLL输出信号中消除干扰信号的技术。 在一方面，消除信号与输入到PLL中的VCO或DCO的信号组合。 在另一方面，通过分析PLL内的一个或多个信号来导出适当的抵消信号。 PLL内的信号可以与一个或多个干扰信号模板（例如具有已知频率的正弦波）相关，以导出一个或多个相关系数。 可以应用系数来加权一个或多个干扰合成功能以产生消除信号。 其他方面提供了从PLL输出端对未知频率的信号的联合分析，合成和消除。
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4.发明授权公开(公告)号：US08076960B2
公开(公告)日：2011-12-13
申请号：US12432468
申请日：2009-04-29
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03C3/0916 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L7/085
摘要： A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain.
摘要翻译： 描述了支持两点调制的数字锁相环（DPLL）。 在一种设计中，DPLL包括一个相位数转换器和一个环路工作的环路滤波器，一个用于低通调制路径的第一处理单元和一个用于高通调制路径的第二处理单元。 第一处理单元接收输入调制信号，并且在相位数转换器之后并且在环路滤波器之前向环路内的第一点提供第一调制信号。 第二处理单元接收输入调制信号，并且在环路滤波器之后向环路内的第二点提供第二调制信号。 第一处理单元可以包括累积输入调制信号以将频率转换为相位的累加器。 第二处理单元可以包括用可变增益来缩放输入调制信号的缩放单元。
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公开(公告)号：US20100310031A1
公开(公告)日：2010-12-09
申请号：US12478506
申请日：2009-06-04
IPC分类号： H03D3/24
CPC分类号： H03L7/08 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L2207/50
摘要： A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a DCO output signal and a reference clock and outputs a first stream of digital values. Quantization noise is reduced by clocking the TDC at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate, thereby reducing digital images. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate, thereby further reducing power consumption.
摘要翻译： 数字锁相环（DPLL）涉及一个时间数字转换器（TDC），它接收DCO输出信号和参考时钟并输出第一个数字值。 通过以较高的速率计时TDC来减少量化噪声。 下采样电路将第一流转换为第二流。 第二流被提供给DPLL的相位检测加法器，使得DPLL的控制部分可以以较低的速率切换以降低功耗。 因此，DPLL被称为多速率DPLL。 由控制部分输出的第三个数字调谐字流在被提供给DCO之前被上采样，从而可以以更高的速率计时DCO，从而减少数字图像。 在接收机应用中，不执行上采样，并且以较低的速率对DCO进行计时，从而进一步降低功耗。
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公开(公告)号：US07974807B2
公开(公告)日：2011-07-05
申请号：US12233400
申请日：2008-09-18
IPC分类号： G06F19/00
CPC分类号： H03L7/091 , H03L2207/50
摘要： Techniques for adaptively calibrating a TDC output signal in a digital phase-locked loop (DPLL). In an exemplary embodiment, a calibration factor multiplied to the TDC output signal is adaptively adjusted to minimize a magnitude function of a phase comparator output signal of the DPLL. In an exemplary embodiment, the calibration factor may be adjusted using an exemplary embodiment of the least-mean squares (LMS) algorithm. Further techniques for simplifying the adaptive algorithm for hardware implementation are described.
摘要翻译： 用于在数字锁相环（DPLL）中自适应校准TDC输出信号的技术。 在示例性实施例中，自适应地调整与TDC输出信号相乘的校准因子以最小化DPLL的相位比较器输出信号的幅度函数。 在示例性实施例中，可以使用最小均方（LMS）算法的示例性实施例来调整校准因子。 描述了用于简化用于硬件实现的自适应算法的进一步的技术。
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公开(公告)号：US20110085589A1
公开(公告)日：2011-04-14
申请号：US12579177
申请日：2009-10-14
IPC分类号： H04B17/00
CPC分类号： H04J11/0083 , H04B17/327 , H04W48/18
摘要： Wireless devices and techniques providing improved system acquisition in an environment of multiple co-existing technologies over a common frequency band are disclosed. In one aspect, at a remote terminal, a power spectral distribution (PSD) of received signals is sequentially measured in contiguous segments of a frequency band of interest. One or more characteristics of the measured PSD is compared to at least one predetermined metric to identify the presence or absence of at least one technology type of the received signals in frequency locations across the band. A system acquisition operation is performed in accordance with the identification, such as a tailored scan of channels at locations where a desired technology is identified.
摘要翻译： 公开了在共同频带上在多个共存技术的环境中提供改进的系统采集的无线设备和技术。 在一个方面，在远程终端，接收信号的功率谱分布（PSD）在感兴趣的频带的连续段中被顺序地测量。 将所测量的PSD的一个或多个特性与至少一个预定的度量进行比较，以识别穿过该频带的频率位置中接收的信号的至少一种技术类型的存在与否。 根据识别执行系统获取操作，例如在识别期望技术的位置处对信道进行定制扫描。
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公开(公告)号：US08433026B2
公开(公告)日：2013-04-30
申请号：US12478506
申请日：2009-06-04
IPC分类号： H03D3/24
CPC分类号： H03L7/08 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L2207/50
摘要： A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a Digitally Controlled Oscillator (DCO) output signal and a reference clock and outputs a first stream of digital values. The TDC is clocked at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate.
摘要翻译： 数字锁相环（DPLL）涉及一个时间数字转换器（TDC），它接收数字控制振荡器（DCO）输出信号和参考时钟并输出第一个数字值。 贸发局的拨款率很高。 下采样电路将第一流转换为第二流。 第二流被提供给DPLL的相位检测加法器，使得DPLL的控制部分可以以较低的速率切换以降低功耗。 因此，DPLL被称为多速率DPLL。 由控制部分输出的第三个数字调谐字流在被提供给DCO之前被上采样，使得DCO可以以更高的速率被计时。 在接收机应用中，不执行上采样，并且DCO以较低速率被计时。
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9.发明申请DIGITAL PHASE-LOCKED LOOP WITH TWO-POINT MODULATION AND ADAPTIVE DELAY MATCHING 有权具有两点调制和自适应延迟匹配的数字相位锁定环公开(公告)号：US20100141313A1
公开(公告)日：2010-06-10
申请号：US12330885
申请日：2008-12-09
IPC分类号： H03L7/06
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0966
摘要： A digital phase-locked loop (DPLL) supporting two-point modulation with adaptive delay matching is described. The DPLL includes highpass and lowpass modulation paths that support wideband and narrowband modulation, respectively, of the frequency and/or phase of an oscillator. The DPLL can adaptively adjust the delay of one modulation path to match the delay of the other modulation path. In one design, the DPLL includes an adaptive delay unit that provides a variable delay for one of the two modulation paths. Within the adaptive delay unit, a delay computation unit determines the variable delay based on a modulating signal applied to the two modulation paths and a phase error signal in the DPLL. An interpolator provides a fractional portion of the variable delay, and a programmable delay unit provides an integer portion of the variable delay.
摘要翻译： 描述了支持具有自适应延迟匹配的两点调制的数字锁相环（DPLL）。 DPLL包括分别支持振荡器的频率和/或相位的宽带和窄带调制的高通和低通调制路径。 DPLL可以自适应地调整一个调制路径的延迟以匹配另一个调制路径的延迟。 在一种设计中，DPLL包括为两个调制路径中的一个提供可变延迟的自适应延迟单元。 在自适应延迟单元内，延迟计算单元基于施加到两个调制路径的调制信号和DPLL中的相位误差信号来确定可变延迟。 内插器提供可变延迟的小数部分，并且可编程延迟单元提供可变延迟的整数部分。
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公开(公告)号：US08391345B2
公开(公告)日：2013-03-05
申请号：US12579177
申请日：2009-10-14
IPC分类号： H04B3/46
CPC分类号： H04J11/0083 , H04B17/327 , H04W48/18
摘要： Wireless devices and techniques providing improved system acquisition in an environment of multiple co-existing technologies over a common frequency band are disclosed. In one aspect, at a remote terminal, a power spectral distribution (PSD) of received signals is sequentially measured in contiguous segments of a frequency band of interest. One or more characteristics of the measured PSD is compared to at least one predetermined metric to identify the presence or absence of at least one technology type of the received signals in frequency locations across the band. A system acquisition operation is performed in accordance with the identification, such as a tailored scan of channels at locations where a desired technology is identified.
摘要翻译： 公开了在共同频带上在多个共存技术的环境中提供改进的系统采集的无线设备和技术。 在一个方面，在远程终端，接收信号的功率谱分布（PSD）在感兴趣的频带的连续段中被顺序地测量。 将所测量的PSD的一个或多个特性与至少一个预定的度量进行比较，以识别穿过该频带的频率位置中接收的信号的至少一种技术类型的存在与否。 根据识别执行系统获取操作，例如在识别期望技术的位置处对信道进行定制扫描。
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