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公开(公告)号：US07710144B2
公开(公告)日：2010-05-04
申请号：US12165804
申请日：2008-07-01
CPC分类号： G06F13/4072 , G06F13/4086
摘要： A memory interface device, system, method, and design structure for controlling for variable impedance and voltage in a memory system are provided. The memory interface device includes a calibration cell configurable to adjust an output impedance relative to an external reference resistor, and driver circuitry including multiple positive drive circuits and multiple negative drive circuits coupled to a driver output in a memory system. The memory interface device further includes impedance control logic to adjust the output impedance of the calibration cell and selectively enable the positive and negative drive circuits as a function of a drive voltage and a target impedance.
摘要翻译： 提供了一种用于控制存储器系统中的可变阻抗和电压的存储器接口设备，系统，方法和设计结构。 存储器接口装置包括可配置为相对于外部参考电阻器调整输出阻抗的校准单元，以及包括耦合到存储器系统中的驱动器输出的多个正驱动电路和多个负驱动电路的驱动器电路。 存储器接口装置还包括阻抗控制逻辑，用于调整校准单元的输出阻抗，并且选择性地使正和负驱动电路作为驱动电压和目标阻抗的函数。
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公开(公告)号：US20100001758A1
公开(公告)日：2010-01-07
申请号：US12165804
申请日：2008-07-01
IPC分类号： H03K17/16 , G11C8/00 , H03K19/0175
CPC分类号： G06F13/4072 , G06F13/4086
摘要： A memory interface device, system, method, and design structure for controlling for variable impedance and voltage in a memory system are provided. The memory interface device includes a calibration cell configurable to adjust an output impedance relative to an external reference resistor, and driver circuitry including multiple positive drive circuits and multiple negative drive circuits coupled to a driver output in a memory system. The memory interface device further includes impedance control logic to adjust the output impedance of the calibration cell and selectively enable the positive and negative drive circuits as a function of a drive voltage and a target impedance.
摘要翻译： 提供了一种用于控制存储器系统中的可变阻抗和电压的存储器接口设备，系统，方法和设计结构。 存储器接口装置包括可配置为相对于外部参考电阻器调整输出阻抗的校准单元，以及包括耦合到存储器系统中的驱动器输出的多个正驱动电路和多个负驱动电路的驱动器电路。 存储器接口装置还包括阻抗控制逻辑，用于调整校准单元的输出阻抗，并且选择性地使正和负驱动电路作为驱动电压和目标阻抗的函数。
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公开(公告)号：US20100321083A1
公开(公告)日：2010-12-23
申请号：US12488767
申请日：2009-06-22
申请人： David J. Chen , William F. Lawson , David W. Mann
发明人： David J. Chen , William F. Lawson , David W. Mann
CPC分类号： H03K19/018521 , Y10T29/49002
摘要： A voltage level translating circuit that allows low voltage signals to be translated to higher voltages, a design structure utilized in the design, manufacture, and/or testing of the voltage level translating circuit, and a method of manufacturing the voltage level translating circuit are described. The translating circuit utilizes two different voltage domains. The high voltage rail of the low voltage domain acts as the ground of the high voltage domain. The translating circuit also utilizes a voltage buffer electrically connected to the high voltage domain and to the low voltage domain to prevent the circuit devices in either domain from seeing too high of a voltage. The translating circuit allows the circuits after the translating circuit to work with signals utilizing the high voltage rail of the high voltage domain.
摘要翻译： 描述了允许将低电压信号转换为更高电压的电压电平转换电路，在电压电平转换电路的设计，制造和/或测试中使用的设计结构以及制造电压电平转换电路的方法 。 转换电路使用两个不同的电压域。 低电压域的高压轨作为高电压域的接地。 转换电路还利用电连接到高电压域和低电压域的电压缓冲器，以防止任一领域中的电路器件看到太高的电压。 转换电路允许转换电路之后的电路利用高电压域的高电压轨来处理信号。
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4.发明授权Apparatus for improved delay voltage level shifting for large voltage differentials 失效用于改善用于大电压差的延迟电压电平移位的装置公开(公告)号：US07301386B2
公开(公告)日：2007-11-27
申请号：US11278236
申请日：2006-03-31
IPC分类号： H03L5/00
CPC分类号： H03K19/018521 , H03K19/01707
摘要： A voltage level shifting device for translating a lower operating voltage to a higher operating voltage includes a first input node coupled to a first pull down device and a second input node coupled to a second pull down device. The second node receives a complementary logic signal with respect to the first input node, the first and second input nodes associated with the lower operating voltage. A first pull up device is in series with the first pull down device and second pull up device is in series with the second pull down device, with the first and second pull up devices coupled to a power supply at the higher operating voltage. An output node is between the second pull down device and the second pull up device, the output node controlling the conductivity of the first pull up device. A clamping device is in parallel with the first pull up device, and configured to prevent the second pull up device from becoming fully saturated.
摘要翻译： 用于将较低工作电压转换到较高工作电压的电压电平移动装置包括耦合到第一下拉装置的第一输入节点和耦合到第二下拉装置的第二输入节点。 第二节点相对于第一输入节点接收互补逻辑信号，第一和第二输入节点与较低工作电压相关联。 第一上拉装置与第一下拉装置串联，第二上拉装置与第二下拉装置串联，第一和第二上拉装置在较高工作电压下耦合到电源。 输出节点位于第二下拉装置和第二上拉装置之间，输出节点控制第一上拉装置的电导率。 夹紧装置与第一上拉装置并联，并且构造成防止第二拉起装置变得完全饱和。
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5.发明授权Implementing linearly weighted thermal coded I/O driver output stage calibration 有权实现线性加权热编码I / O驱动器输出级校准公开(公告)号：US08766663B2
公开(公告)日：2014-07-01
申请号：US13526004
申请日：2012-06-18
申请人： David J. Chen , William F. Lawson
发明人： David J. Chen , William F. Lawson
IPC分类号： H03K19/003 , G06F17/50
CPC分类号： H03K19/0005
摘要： A method and circuit for implementing calibration of a linearly weighted, thermal coded I/O driver output stage, and a design structure on which the subject circuit resides are provided. The circuit includes a PFET calibration impedance matching function determining calibration PVTP bits for calibrating output stage PFETs of the linearly weighted, thermal coded I/O driver output stage, an NFET calibration impedance matching function determining calibration bits PVTN for calibrating output stage NFETs of the linearly weighted, thermal coded I/O driver output stage once the PFET calibration is complete and an output latch function providing the calibration PVTP and PVTN outputs for the I/O driver output stage to match an impedance of an external calibration resistor. A clock logic function generates an output latch clock and an internal reset signal completing calibration.
摘要翻译： 一种用于实现线性加权的热编码I / O驱动器输出级的校准的方法和电路以及设置有被摄体电路的设计结构。 该电路包括PFET校准阻抗匹配功能，确定用于校准线性加权的热编码I / O驱动器输出级的输出级PFET的校准PVTP位，NFET校准阻抗匹配函数确定用于校准线性的输出级NFET的校准位PVTN 一旦PFET校准完成并且输出锁存功能为I / O驱动器输出级提供校准PVTP和PVTN输出以匹配外部校准电阻器的阻抗，则加权，热编码的I / O驱动器输出级。 时钟逻辑功能产生输出锁存时钟和内部复位信号完成校准。
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6.发明申请IMPLEMENTING LINEARLY WEIGHTED THERMAL CODED I/O DRIVER OUTPUT STAGE CALIBRATION 有权实施线性加权热编码I / O驱动器输出级校准公开(公告)号：US20130335114A1
公开(公告)日：2013-12-19
申请号：US13526004
申请日：2012-06-18
申请人： David J. Chen , William F. Lawson
发明人： David J. Chen , William F. Lawson
IPC分类号： H03K19/003 , G06F17/50
CPC分类号： H03K19/0005
摘要： A method and circuit for implementing calibration of a linearly weighted, thermal coded I/O driver output stage, and a design structure on which the subject circuit resides are provided. The circuit includes a PFET calibration impedance matching function determining calibration PVTP bits for calibrating output stage PFETs of the linearly weighted, thermal coded I/O driver output stage, an NFET calibration impedance matching function determining calibration bits PVTN for calibrating output stage NFETs of the linearly weighted, thermal coded I/O driver output stage once the PFET calibration is complete and an output latch function providing the calibration PVTP and PVTN outputs for the I/O driver output stage to match an impedance of an external calibration resistor. A clock logic function generates an output latch clock and an internal reset signal completing calibration.
摘要翻译： 一种用于实现线性加权的热编码I / O驱动器输出级的校准的方法和电路以及设置有被摄体电路的设计结构。 该电路包括PFET校准阻抗匹配功能，确定用于校准线性加权的热编码I / O驱动器输出级的输出级PFET的校准PVTP位，NFET校准阻抗匹配函数确定用于校准线性的输出级NFET的校准位PVTN 一旦PFET校准完成并且输出锁存功能为I / O驱动器输出级提供校准PVTP和PVTN输出以匹配外部校准电阻器的阻抗，则加权，热编码的I / O驱动器输出级。 时钟逻辑功能产生输出锁存时钟和内部复位信号完成校准。
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公开(公告)号：US08581498B1
公开(公告)日：2013-11-12
申请号：US13370884
申请日：2012-02-10
CPC分类号： H05B33/0815
摘要： Methods and apparati for controlling bleed current (IBLEED) in a driver circuit (20) for a lighting device (23). A method embodiment of the present invention comprises the steps of coupling a dimmer (21) to an input of the driver circuit (20), and forcing the bleed current (IBLEED) to be inversely proportional to the time-averaged voltage (VLEDP) at said lighting device (23). The dimmer (21) consumes power even when the lighting device (23) is not emitting light.
摘要翻译： 用于控制用于照明装置（23）的驱动电路（20）中的放电电流（IBLEED）的方法和装置。 本发明的方法实施例包括以下步骤：将调光器（21）耦合到驱动器电路（20）的输入端，并迫使放电电流（IBLEED）与时间平均电压（VLEDP）成反比， 所述照明装置（23）。 即使照明装置（23）不发光，调光器（21）也消耗功率。
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8.发明授权DNA dependent protein kinase catalytic subunit phosphorylation sites and antibodies thereto 有权DNA依赖性蛋白激酶催化亚基磷酸化位点及其抗体公开(公告)号：US07491804B2
公开(公告)日：2009-02-17
申请号：US10511561
申请日：2003-04-21
IPC分类号： C07K16/40
CPC分类号： C07K16/44 , C07K16/40 , C12N9/1205 , C12Y207/01037 , G01N33/5014 , G01N33/573 , G01N2333/9121 , G01N2800/52
摘要： The identification and use of two major DNA-PKcs autophosphorylation sites. Threonine (T) 2609 and Serine (S) 2056, including antibodies specific for phosphorylated T2609 and 52056. Peptides and polynucleotides encoding same, that feature these two sites of phosphorylation. The antibodies do not bind to the unphosphorylated DNA-PKcs protein or peptide, thus providing diagnostic tools to monitor the effectiveness of treatments which target the DNA repair pathway of cancer cells, and the ability to intervene or inhibit in phosphorylation of T2609 or 52056, either through application of a drug or an antibody, to increase the radiosensitivity of cancer cells.
摘要翻译： 鉴定和使用两个主要的DNA-PKcs自磷酸化位点。 苏氨酸（T）2609和丝氨酸（S）2056，包括对磷酸化的T2609和52056特异的抗体。编码相同的肽和多核苷酸，其特征在于这两个磷酸化位点。 抗体不结合未磷酸化的DNA-PKcs蛋白或肽，从而提供诊断工具来监测靶向癌细胞的DNA修复途径的治疗的有效性，以及介导或抑制T2609或52056磷酸化的能力， 通过施用药物或抗体来增加癌细胞的放射敏感性。
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