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1.发明申请CONFIGURABLE PRE-EMPHASIS DRIVER WITH SELECTIVE CONSTANT AND ADJUSTABLE OUTPUT IMPEDANCE MODES 失效具有选择性恒定和可调输出阻抗模式的可配置的前置驱动器公开(公告)号：US20100177830A1
公开(公告)日：2010-07-15
申请号：US12354007
申请日：2009-01-15
IPC分类号： H04B3/00
CPC分类号： H04B3/145
摘要： Embodiments of the invention are directed to a single driver that can be used to transmit data with configurable levels of pre-emphasis, and can have either a constant or adjustable driver output impendence, selectively. One embodiment, directed to a driver apparatus, is associated with a digital communication channel for transmitting data signals, wherein at least one of the signals includes a higher frequency component. The apparatus comprises a first sub-driver that has a constant output impedance, and is selectively configurable to implement two or more different levels of pre-emphasis. The apparatus further comprises one or more second sub-drivers. A set of connector elements are provided for connecting the first sub-driver and each of the second sub-drivers in parallel relationship with one another, so that the first sub-driver and each of the second sub-drivers all have inputs that respectively receive a specified driver apparatus input signal, and all have outputs that are connected together to selectively provide a specified driver apparatus output impedance. The apparatus further includes a device that is connected to selectively disable and enable each of the second sub-drivers.
摘要翻译： 本发明的实施例涉及可用于传输具有可配置水平的预加重的数据的单个驱动器，并且可以选择性地具有恒定的或可调节的驱动器输出阻抗。 针对驱动器装置的一个实施例与用于传输数据信号的数字通信信道相关联，其中信号中的至少一个包括较高频率分量。 该装置包括具有恒定输出阻抗的第一子驱动器，并且可选择性地配置为实现两个或多个不同级别的预加重。 该装置还包括一个或多个第二子驱动器。 提供了一组连接器元件，用于将第一子驱动器和每个第二子驱动器彼此并联连接，使得第一子驱动器和每个第二子驱动器都具有分别接收的输入 指定的驱动器装置输入信号，并且都具有连接在一起的输出，以选择性地提供指定的驱动器装置输出阻抗。 该装置还包括被连接以选择性地禁用并启用每个第二子驱动器的装置。
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2.发明授权Configurable pre-emphasis driver with selective constant and adjustable output impedance modes 失效可配置预加重驱动器，具有选择性恒定和可调输出阻抗模式公开(公告)号：US07888968B2
公开(公告)日：2011-02-15
申请号：US12354007
申请日：2009-01-15
IPC分类号： H03K19/094 , H03K17/16
CPC分类号： H04B3/145
摘要： Embodiments of the invention are directed to a single driver that can be used to transmit data with configurable levels of pre-emphasis, and can have either a constant or adjustable driver output impendence, selectively. One embodiment, directed to a driver apparatus, is associated with a digital communication channel for transmitting data signals, wherein at least one of the signals includes a higher frequency component. The apparatus comprises a first sub-driver that has a constant output impedance, and is selectively configurable to implement two or more different levels of pre-emphasis. The apparatus further comprises one or more second sub-drivers. A set of connector elements are provided for connecting the first sub-driver and each of the second sub-drivers in parallel relationship with one another, so that the first sub-driver and each of the second sub-drivers all have inputs that respectively receive a specified driver apparatus input signal, and all have outputs that are connected together to selectively provide a specified driver apparatus output impedance. The apparatus further includes a device that is connected to selectively disable and enable each of the second sub-drivers.
摘要翻译： 本发明的实施例涉及可用于传输具有可配置水平的预加重的数据的单个驱动器，并且可以选择性地具有恒定的或可调节的驱动器输出阻抗。 针对驱动器装置的一个实施例与用于传输数据信号的数字通信信道相关联，其中信号中的至少一个包括较高频率分量。 该装置包括具有恒定输出阻抗的第一子驱动器，并且可选择性地配置为实现两个或多个不同级别的预加重。 该装置还包括一个或多个第二子驱动器。 提供了一组连接器元件，用于将第一子驱动器和每个第二子驱动器彼此并联连接，使得第一子驱动器和每个第二子驱动器都具有分别接收的输入 指定的驱动器装置输入信号，并且都具有连接在一起的输出，以选择性地提供指定的驱动器装置输出阻抗。 该装置还包括被连接以选择性地禁用并启用每个第二子驱动器的装置。
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公开(公告)号：US07212035B2
公开(公告)日：2007-05-01
申请号：US11055834
申请日：2005-02-11
IPC分类号： H03K19/0175
CPC分类号： H03K19/0005
摘要： A line driver for off-chip communication comprises multiple parallel stages each with separate inputs. The parallel stages each have a controlled impedance when driving the line driver output node to a logic zero or a logic one. A line driver controller is used to select what combination of driver stages are used to drive the output node based on whether the output node is transitioning between logic state or is remaining static. During power-up, a test program tries different combinations of driver stages for particular symbol patterns and determines what is the optimal ratio between line driver resistance for the dynamic and static cases and stores the optimum combination. The data stream feeding the line driver is sampled in real time to determine the transition states and selects the optimal number of driver stages for each case.
摘要翻译： 用于片外通信的线路驱动器包括多个并行级，每个并行级具有单独的输入。 当将线路驱动器输出节点驱动到逻辑0或逻辑1时，并联级各自具有受控阻抗。 线路驱动器控制器用于基于输出节点是在逻辑状态之间转换还是保持静态来选择驱动器级的组合来驱动输出节点。 在上电期间，测试程序尝试针对特定符号模式的驱动器级的不同组合，并确定动态和静态情况下线驱动器电阻之间的最佳比例是多少，并存储最佳组合。 馈送线路驱动器的数据流被实时采样以确定转换状态，并为每种情况选择最佳数量的驱动级。
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公开(公告)号：US20080137250A1
公开(公告)日：2008-06-12
申请号：US11567794
申请日：2006-12-07
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： A protection circuit with a positive field effect transistor coupled to a power source, a negative field effect transistor connected to a pass-gate and a circuit ground, a circuit input terminal, a multi-level source of protection voltage coupled to an external circuit and at least three additional field effect transistors. A drain of the negative field effect transistor couples to a gate of the positive field effect transistor. When the circuit input terminal is low the pass-gate is on; when the circuit input terminal is high the pass-gate is off. Embodiments of the invention also include stacks of three or more field effect transistors.
摘要翻译： 具有耦合到电源的正场效应晶体管的保护电路，连接到通过栅极和电路接地的负场效应晶体管，电路输入端子，耦合到外部电路的多电平保护电压源，以及 至少三个附加场效应晶体管。 负场效应晶体管的漏极耦合到正场效应晶体管的栅极。 当电路输入端子为低电平时，通路导通; 当电路输入端子为高电平时，通电门断开。 本发明的实施例还包括三个或更多个场效应晶体管的堆叠。
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5.发明授权公开(公告)号：US07821300B2
公开(公告)日：2010-10-26
申请号：US12327786
申请日：2008-12-03
IPC分类号： H03K19/086 , H03B1/00
CPC分类号： H03K19/018528 , H03K19/09436
摘要： A system includes a first CML buffer configured to receive a first bias signal and a first CML signal of a first CML logic family. The first CML buffer produces a second CML signal of the first CML logic family based on the first CML signal and the first bias signal. A first coupling capacitor module couples to the first CML buffer. The first coupling capacitor module receives the second CML signal and produces a third CML signal based on the second CML signal. A second CML buffer couples to the coupling capacitor module and receives a second bias signal and the third CML signal, producing a fourth CML signal of a second CML logic family. A feedback module couples to the second CML buffer and receives the fourth CML signal producing a fifth CML signal. The second CML buffer is produces the fourth CML signal based on the second bias signal, the third CML signal, and the fifth CML signal.
摘要翻译： 系统包括被配置为接收第一CML逻辑系列的第一偏置信号和第一CML信号的第一CML缓冲器。 第一CML缓冲器基于第一CML信号和第一偏置信号产生第一CML逻辑系列的第二CML信号。 第一耦合电容器模块耦合到第一CML缓冲器。 第一耦合电容器模块接收第二CML信号并且基于第二CML信号产生第三CML信号。 第二CML缓冲器耦合到耦合电容器模块并且接收第二偏置信号和第三CML信号，产生第二CML逻辑系列的第四CML信号。 反馈模块耦合到第二CML缓冲器并且接收产生第五CML信号的第四CML信号。 第二CML缓冲器基于第二偏置信号，第三CML信号和第五CML信号产生第四CML信号。
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公开(公告)号：US07457091B2
公开(公告)日：2008-11-25
申请号：US11567794
申请日：2006-12-07
IPC分类号： H02H3/20
CPC分类号： H02H9/046
摘要： A protection circuit with a positive field effect transistor coupled to a power source, a negative field effect transistor connected to a pass-gate and a circuit ground, a circuit input terminal, a multi-level source of protection voltage coupled to an external circuit and at least three additional field effect transistors. A drain of the negative field effect transistor couples to a gate of the positive field effect transistor. When the circuit input terminal is low the pass-gate is on; when the circuit input terminal is high the pass-gate is off. Embodiments of the invention also include stacks of three or more field effect transistors.
摘要翻译： 具有耦合到电源的正场效应晶体管的保护电路，连接到通过栅极和电路接地的负场效应晶体管，电路输入端子，耦合到外部电路的多电平保护电压源，以及 至少三个附加场效应晶体管。 负场效应晶体管的漏极耦合到正场效应晶体管的栅极。 当电路输入端子为低电平时，通路导通; 当电路输入端子为高电平时，通电门断开。 本发明的实施例还包括三个或更多个场效应晶体管的堆叠。
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7.发明申请公开(公告)号：US20080143375A1
公开(公告)日：2008-06-19
申请号：US11611200
申请日：2006-12-15
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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8.发明授权公开(公告)号：US07477068B2
公开(公告)日：2009-01-13
申请号：US12058689
申请日：2008-03-29
IPC分类号： H03K17/16
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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9.发明授权公开(公告)号：US07382151B1
公开(公告)日：2008-06-03
申请号：US11611200
申请日：2006-12-15
IPC分类号： H03K17/16
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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公开(公告)号：US20100134145A1
公开(公告)日：2010-06-03
申请号：US12327786
申请日：2008-12-03
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528 , H03K19/09436
摘要： A system includes a first CML buffer configured to receive a first bias signal and a first CML signal of a first CML logic family. The first CML buffer produces a second CML signal of the first CML logic family based on the first CML signal and the first bias signal. A first coupling capacitor module couples to the first CML buffer. The first coupling capacitor module receives the second CML signal and produces a third CML signal based on the second CML signal. A second CML buffer couples to the coupling capacitor module and receives a second bias signal and the third CML signal, producing a fourth CML signal of a second CML logic family. A feedback module couples to the second CML buffer and receives the fourth CML signal producing a fifth CML signal. The second CML buffer is produces the fourth CML signal based on the second bias signal, the third CML signal, and the fifth CML signal.
摘要翻译： 系统包括被配置为接收第一CML逻辑系列的第一偏置信号和第一CML信号的第一CML缓冲器。 第一CML缓冲器基于第一CML信号和第一偏置信号产生第一CML逻辑系列的第二CML信号。 第一耦合电容器模块耦合到第一CML缓冲器。 第一耦合电容器模块接收第二CML信号并且基于第二CML信号产生第三CML信号。 第二CML缓冲器耦合到耦合电容器模块并且接收第二偏置信号和第三CML信号，产生第二CML逻辑系列的第四CML信号。 反馈模块耦合到第二CML缓冲器并且接收产生第五CML信号的第四CML信号。 第二CML缓冲器基于第二偏置信号，第三CML信号和第五CML信号产生第四CML信号。
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