公开(公告)号：US5847558A

公开(公告)日：1998-12-08

申请号：US700702

申请日：1996-07-10

申请人： Daniel McGuire ,  David Bytheway

发明人： Daniel McGuire ,  David Bytheway

IPC分类号： G01R25/04

CPC分类号： G01R25/04

摘要： A signal sampling circuit receives a clock signal indicative of a sampling rate and a periodic input signal to produce a digitized sampled output signal. The sampled signal is applied to an all-pass filter having a single pole/zero pair in which the pole/zero values are determined by a number supplied by a number generator. The number generator varies the applied number in a random or pseudorandom fashion to create a correspondingly random or pseudorandom variation of the transfer function of the filter. The filtered sample signal is then further processed by an absolute value operator and an average value operator for application to an amplitude responsive device such as a meter. The random or pseudorandom variation of the filter transfer function introduces a corresponding random or pseudorandom variation of the phase shift imposed upon the sampled signal within the filter. This. phase shift operates to impede or preclude the generation of erroneous beat note amplitude variations within the sampled signal for input signals having frequencies at or near the sampling rate or submultiples thereof.

摘要翻译： 信号采样电路接收指示采样率的时钟信号和周期性输入信号以产生数字化的采样输出信号。 采样信号被施加到具有单极/零对的全通滤波器，其中极/零值由数字发生器提供的数字确定。 数字发生器以随机或伪随机方式改变所应用的数量，以产生滤波器的传递函数的相应的随机或伪随机变化。 滤波后的采样信号然后由绝对值运算符和用于应用于诸如仪表的振幅响应装置的平均值运算符进一步处理。 滤波器传递函数的随机或伪随机变化引入了对滤波器内采样信号施加的相移的相应随机或伪随机变化。 这个。 相移操作以阻止或排除在具有或接近采样速率或其次数的频率的输入信号的采样信号内产生错误的拍音振幅变化。

公开(公告)号：US20060120342A1

公开(公告)日：2006-06-08

申请号：US10518212

申请日：2003-06-13

申请人： Carl Christensen ,  David Bytheway ,  Mitchell Hayden

发明人： Carl Christensen ,  David Bytheway ,  Mitchell Hayden

IPC分类号： H04L12/28

CPC分类号： H04L45/16 ,  H04L45/00 ,  H04L45/583 ,  H04L45/60 ,  H04L49/15 ,  H04L49/201 ,  H04L49/203 ,  H04L49/205 ,  H04L49/206 ,  H04L49/25 ,  H04L49/30 ,  H04L49/45 ,  H04L49/552 ,  H04L2012/5664

摘要： A fully redundant linearly expandable router is comprised of first, second, third and fourth router components. Each router component includes first and second routing engines. First, second and third discrete links couple the first routing engine to the first routing engines, respectively. Fourth and fifth discrete links couple the first routing engine to the first routing engines, respectively. A sixth discrete link couples the routing engine to the routing engine. Seventh, eighth and ninth discrete links couple the second routing engine to the second routing engines, respectively. Tenth and eleventh discrete links couple the second routing engine to the second routing engines, respectively. A twelfth discrete link couples the routing engine to the router engine.

摘要翻译： 完全冗余的线性扩展路由器由第一，第二，第三和第四路由器组件组成。 每个路由器组件包括第一和第二路由引擎。 首先，第二和第三离散链路分别将第一路由引擎耦合到第一路由引擎。 第四和第五离散链路分别将第一路由引擎耦合到第一路由引擎。 第六个离散链路将路由引擎耦合到路由引擎。 第七，第八和第九离散链路分别将第二路由引擎耦合到第二路由引擎。 第十和第十一离散链路分别将第二路由引擎耦合到第二路由引擎。 第十二个离散链路将路由引擎耦合到路由器引擎。

公开(公告)号：US20050175017A1

公开(公告)日：2005-08-11

申请号：US10518580

申请日：2003-06-17

申请人： Carl Christensen ,  David Bytheway

发明人： Carl Christensen ,  David Bytheway

IPC分类号： H04L12/775 ,  H04J3/06 ,  H04L12/18 ,  H04L12/28 ,  H04M3/12 ,  H04Q1/02 ,  H04Q3/52

CPC分类号： H04J3/0688 ,  H04J3/0685 ,  H04L45/28 ,  H04L45/583 ,  H04L45/60 ,  H04M3/12 ,  H04M2201/14 ,  H04Q3/521 ,  H04Q2213/13003 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13167 ,  H04Q2213/13214 ,  H04Q2213/13242 ,  H04Q2213/1334 ,  H04Q2213/13341

摘要： Supportably mounted by each chassis of a multi-chassis broadcast router are primary router matrix cards, redundant router matrix cards and clock-demanding input and output cards. A first master clock firesides on the primary router matrix card of a first chassis while a second master clock firesides on the redundant router matrix card of a second chassis. Each master clock is configured to provide a respective common clock signal to all of the input and output cards of the first and second chassis. Control logic determines whether the first master clock or the second master clock issues the common clock signal.

摘要翻译： 主机路由器矩阵卡，冗余路由器矩阵卡和需要时钟要求的输入和输出卡可支持由多机架广播路由器的每个机箱安装。 第一主机时钟在第一机箱的主路由器矩阵卡上闪烁，而第二主时钟在第二机箱的冗余路由器矩阵卡上发火。 每个主时钟被配置为向第一和第二机箱的所有输入和输出卡提供相应的公共时钟信号。 控制逻辑确定第一主时钟或第二主时钟是否发出公共时钟信号。

公开(公告)号：US20080052552A1

公开(公告)日：2008-02-28

申请号：US11628807

申请日：2005-06-01

申请人： Carl Christensen ,  David Bytheway ,  Lynn Arbuckle ,  Randall Redondo

发明人： Carl Christensen ,  David Bytheway ,  Lynn Arbuckle ,  Randall Redondo

IPC分类号： G06F1/12

CPC分类号： G06F1/10

摘要： A router, for routing at least one input signal to at least one output, comprises at least one input module and at least one output module. Each of the input and output modules includes at least one clock selector circuit for selecting from among a first and second clock signal, and an oscillator signal, as a common output clock signal for the at least first router, based in part on whether at least one of the first and second clock signals has toggled. The clock selector circuit provides redundancy as well as distribution of clock signals among elements within each module.

摘要翻译： 用于将至少一个输入信号路由到至少一个输出的路由器包括至少一个输入模块和至少一个输出模块。 每个输入和输出模块包括至少一个用于从第一和第二时钟信号中选择的时钟选择器电路和作为至少第一路由器的公共输出时钟信号的振荡器信号，部分基于至少是否 第一和第二个时钟信号之一已切换。 时钟选择器电路在每个模块内的元件之间提供冗余以及时钟信号的分配。

公开(公告)号：US20050243710A1

公开(公告)日：2005-11-03

申请号：US10518670

申请日：2003-06-13

申请人： Carl Christensen ,  Marc Walker ,  David Blair ,  David Bytheway ,  Lynn Arbuckle

发明人： Carl Christensen ,  Marc Walker ,  David Blair ,  David Bytheway ,  Lynn Arbuckle

IPC分类号： H04L1/00 ,  G01R31/08 ,  G06F11/00 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/20 ,  H04L1/22 ,  H04L12/18 ,  H04L12/26 ,  H04L12/28 ,  H04L12/56

CPC分类号： H04L1/22 ,  H04L1/0061 ,  H04L12/1868 ,  H04L45/60 ,  H04L49/201 ,  H04L49/206 ,  H04L49/557

摘要： A fault-tolerant router first and second router matrix card. The first and second router matrix cards receive a common set of 4n parity encoded input digital audio data streams and respectively generates therefrom, first and second sets of M output digital audio streams. As the first and second sets of data streams propagate along the first and second router matrix cards, respectively, one or more health bits are set whenever an error or other type of fault condition is detected. First and second parity check circuits are configured to detect parity errors and/or assess the relative health of the first and second sets of data streams and one of the two sets of data streams is selected as the output of the fault-tolerant router based upon either the parity error analysis, health analysis or both.

摘要翻译： 容错路由器第一和第二路由器矩阵卡。 第一和第二路由器矩阵卡接收一组共同的4n个奇偶编码的输入数字音频数据流，并分别由M个输出数字音频流的第一和第二组生成。 当第一和第二组数据流分别沿着第一和第二路由器矩阵卡传播时，每当检测到错误或其他类型的故障状况时，就设置一个或多个健康位。 第一和第二奇偶校验电路被配置为检测奇偶校验错误和/或评估第一和第二组数据流的相对健康状况，并且两组数据流中的一组被选择为基于容错路由器的输出 奇偶校验错误分析，健康分析或两者。

公开(公告)号：US20050207428A1

公开(公告)日：2005-09-22

申请号：US10518211

申请日：2003-06-16

申请人： Carl Christensen ,  David Bytheway ,  Mitchell Hayden

发明人： Carl Christensen ,  David Bytheway ,  Mitchell Hayden

IPC分类号： H04L12/18 ,  H04L12/54 ,  H04L12/56

CPC分类号： H04L45/586 ,  H04L12/54 ,  H04L45/00 ,  H04L45/16

摘要： A linearly expandable router is comprised of first, second, third and fourth router components. First, second and third discrete links couple an input side of a routing engine of the first router component (102) to an input side of a routing engine of the second, third and fourth router components. Similarly, fourth and fifth discrete links couple the input side of the routing engine for the second router component to the input side of the routing engine of the third and fourth router components, respectively. Finally, a sixth discrete link couples the input side of the routing engine for the third router component to the input side of the router engine for the fourth router component.

摘要翻译： 线性扩展路由器由第一，第二，第三和第四路由器组件组成。 首先，第二和第三离散链路将第一路由器组件（102）的路由引擎的输入端耦合到第二，第三和第四路由器组件的路由引擎的输入侧。 类似地，第四和第五离散链路将第二路由器组件的路由引擎的输入侧分别耦合到第三和第四路由器组件的路由引擎的输入侧。 最后，第六个离散链路将用于第三路由器组件的路由引擎的输入侧耦合到用于第四路由器组件的路由器引擎的输入侧。