公开(公告)号：US07519889B1

公开(公告)日：2009-04-14

申请号：US12060339

申请日：2008-04-01

申请人： Daniel W. Cervantes ,  Joshua P. Hernandez ,  Tung N. Pham ,  Timothy M. Skergan

发明人： Daniel W. Cervantes ,  Joshua P. Hernandez ,  Tung N. Pham ,  Timothy M. Skergan

IPC分类号： G01R31/28

CPC分类号： G01R31/318385

摘要： A method to reduce logic built in self test manufacturing test time of integrated circuits, comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array locally disposed on an integrated circuit, each of the plurality of test seeds is associated with a set of LBIST control information; sending the plurality of test seeds from the locally accessible on-chip memory array repetitively into a pseudo-random pattern generator one at a time during an LBIST operation being under the control from the set of LBIST control information; generating random bit streams serially into a plurality of parallel shift registers of the integrated circuit through the use of the plurality of test seeds; and performing a logic built-in self test on a plurality of logic blocks in the integrated circuit to detect defects within the integrated circuit.

摘要翻译： 一种减少集成电路的自检制造测试时间内置逻辑的方法，其特征在于包括：将大量测试种子加载到本地可访问的本地设置在集成电路上的片上存储器阵列中， 与一组LBIST控制信息相关联; 在LBIST控制信息的集合控制下的LBIST操作期间，一次一个地将多个测试种子从本地可访问的片上存储器阵列发送到伪随机模式生成器中; 通过使用多个测试种子将随机比特流串行地生成到集成电路的多个并行移位寄存器中; 以及对所述集成电路中的多个逻辑块执行逻辑内置自检以检测所述集成电路内的缺陷。

公开(公告)号：US5336627A

公开(公告)日：1994-08-09

申请号：US4088

申请日：1993-01-13

申请人： Thierry Pacou ,  Patrice Arsene-Henry ,  Tung N. Pham ,  Yann Genuist

发明人： Thierry Pacou ,  Patrice Arsene-Henry ,  Tung N. Pham ,  Yann Genuist

IPC分类号： H01L29/812 ,  H01L21/266 ,  H01L21/336 ,  H01L21/338

CPC分类号： H01L29/66878 ,  H01L21/266 ,  H01L29/66659

摘要： The disclosure relates to the making of the source and drain access regions of a field-effect transistor, these two regions being differentiated. The control region is defined by means of a three-layer mask of metal, resin and metal. A resin mask protects the drain access region, thus enabling the implantation of the source access region. After the dissolving of the resins, the drain access region is implanted.

摘要翻译： 本公开涉及制造场效应晶体管的源极和漏极访问区域，这两个区域是不同的。 通过金属，树脂和金属的三层掩模来限定控制区域。 树脂掩模保护漏极接近区域，从而能够植入源极接近区域。 树脂溶解后，注入漏极通路区域。